Paper

D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara, "Multidimensional Support Vector Machines for Visualization of Gene Expression Data", Bioinfomatics, Vol.21, No. 4 pp.439-444, 2005
M. Kondo and H. Nakamura, "Small, Fast and Low-Power Register File by Bit-Partitioning", Proceedings of HPCA-11, pp.40-49, Feb. 2005
中島浩，中村宏，佐藤三久，朴泰祐，松岡聡，"高性能計算のための低電力・高密度クラスタMegaProto" 情報処理学会研究報告-ARC-162(21) HPC-101(21), pp.121-126, 2005
藤田元信、近藤正章、中村宏，"ソフトウェア制御オンチップメモリにおける演算処理を考慮した低消費電力化手法" 情報処理学会研究報告-ARC-162(35) HPC-101(35), pp.205-210, 2005
Nattha Jindapetch, Hiroshi Saito, Krerkchai Thongnoo and Takashi Nanya, "A Fair Overhead Comparison Between Asynchronous Four-Phase Protocol Based Controllers and Local Clock Controllers," 2005 ECTI International Conference (May 2005)
M.Imai, C.Kogure, T.Nanya, "A novel design method using delay-variation-aware cell libraries for asynchronous bundled-data transfer circuits," ITC-CSCC, pp.441-442 (Korea, July 2005)
H.Saito, N.Jindapetch, T.Yoneda, C.Meyers, T.Nanya, "A scheduling method for asynchronous bundled-data implementations based on the completion of data operations," ITC-CSCC, pp.433-434 (July, 2005)
M.Tsukisaka, M.Imai, T.Nanya, "Single Latched Scan Registers based on Multi-Clock for Low Heat Dissipation and for Low IR-Drop," ITC-CSCC, Vol.3, pp.945-946 (July, 2005)
M. Kondo and H. Nakamura, "Dynamic Processor Throttling for Power Efficient Computations", PACS2004 (Power-Aware Computer Systems), LNCS Vol.3471, pp. 120-134, Vol.3471, 2005
H. Nakashima, H. Nakamura, M. Sato, T. Boku, S. Matsuoka, D. Takahashi, and Y. Hotta, "MegaProto: a low-power and compact cluster for high-performance computing", Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS-2005) HP-PAC Workshop (CD-ROM), April, 2005
K. Kurata, H. Nakamura and V. Breton, "Secret Sequence Comparison on Public Grid Computing Resources", Proceedings of CCGrid2005, pp.832-839, May, 2005
H. Sasaki, M. Kondo, and H. Nakamura, "Dynamic Instruction Cascading on GALS Microprocessor", PATMOS2005, Lecture Notes in Computer Science, pp30-39, Vol 3728, Springer-Verlag, 2005
H. Nakashima, H. Nakamura, M. Sato, T. Boku, S. Matsuoka, D. Takahashi, and Y. Hotta, "MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology", Proceedings of SC05, (CD-ROM), Nov. 2005
中島浩，中村宏，佐藤三久，朴泰祐，松岡聡， "高性能計算のための低電力・高密度クラスタMegaProto", 情報処理学会研究報告-ARC-162(21) HPC-101(21), pp.121-126, 2005
藤田元信、近藤正章、中村宏， "ソフトウェア制御オンチップメモリにおける演算処理を考慮した低消費電力化手法", 情報処理学会研究報告-ARC-162(35) HPC-101(35), pp.205-210, 2005
近藤正章、中村宏， "CMP向け動的電源電圧・周波数制御手法の提案", 情報処理学会研究報告-ARC-163(6), pp.25-30, 2005
渡辺亮、近藤正章、今井雅、中村宏、南谷崇， "GALS型SoCの低消費電力化のためのタスクスケジューリング手法", 情報処理学会研究報告-ARC-164(11), pp.61-66, 2005 (SWoPP2005)
佐々木広、近藤正章、中村宏， "GALSマイクロプロセッサにおける動的命令カスケーディング", 情報処理学会研究報告-ARC-164(12), pp.67-72, 2005 (SWoPP2005)
東美和子、近藤正章、今井雅、中村宏、南谷崇、 "空間的・時間的な故障率の変動を考慮したチェックポインティング手法の初期検討", 信学技報DC2005-14(2005-08), pp.7-12, 2005 (SWoPP2005)
近藤正章、中村宏、 "めりはり型実行モデルに基づくアーキテクチャ", 情報処理学会研究報告 2005-ARC-165、pp.73-74、2005 (DesignGaia)
今井雅、渡邊孝一、近藤正章、中村宏、南谷崇、 "遅延変動特性を考慮したタイミング信号設計方式に関する検討", 信学技報 ICD2005-154、pp.31-36、2005 (DesignGaia)
渡邊孝一、今井雅、近藤正章、中村宏、南谷崇、 "bit単位の遅延変動を考慮した高性能低消費電力演算回路の設計", 信学技報 ICD2005-155、pp.37-42、2005 (DesignGaia)
近藤正章、中村宏、 "DVFSを用いたチップマルチプロセッサ向け高性能・低電力化手法", 信学技報ICD2005-186(2005-12), pp.19-24, 2005
佐々木広、近藤正章、中村宏， "動的命令カスケーディングによるGALS型マイクロプロセッサの高性能", 信学技報ICD2005-185(2005-12), pp.13-18, 2005

藤田元信, 田中慎一, 近藤正章, 中村宏, "ソフトウェア制御オンチップメモリにおけるスタティック消費電力削減手法", 情報処理学会論文誌コンピューティングシステム, Vol.45, No.SIG11(ACS7), pp. 219-228, 2004
堀田義彦, 佐藤三久, 朴泰祐, 高橋大介, 中島佳宏, 高橋睦史, 中村宏, "プロセッサの消費電力測定と低消費電力プロセッサによるクラスタの検討", 情報処理学会論文誌コンピューティングシステム, Vol.45, No.SIG11(ACS7), pp. 207-218, 2004
N. Jacq, C. Blanchet, E. Cornillot, K. Kurata, H. Nakamura, T. Sylvestre, V. Breton, "GRID AS A BIOINFORMATIC TOOL", Parallel Computing, Vol.30, pp.1093-1107, 2004
D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara. "Multidimensional support vector machines for visualization of gene expression data". Proceedings of ACM Symposium on Applied Computing, pp. 175-179, March 2004.
M.Imai, M.Ozcan, T.Nanya: "Evaluation of Delay Variance in Asynchronous Circuits based on the Scalable-Delay-Insensitive Model" in Proc. ASYNC2004, pp.62-71 (April 2004)
H.Saito, H.Nakamura, M Fujita, T,Nanya:"Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods," in IPSJ Jounal, Vol.45, No.5. pp.1289-1299(2004 May)
藤田元信、田中慎一、近藤正章、中村宏、"ソフトウェア制御オンチップメモリにおけるスタティック消費電力削減手法", 先進的計算基盤システムシンポジウムSACSIS2004, pp. 3-10, May, 2004
田島裕也、林田卓朗、近藤正章、今井雅、中村宏、南谷崇、"多重故障に適応したSkewed Checkpointing の提案", 先進的計算基盤システムシンポジウムSACSIS2004, pp. 153-154, May, 2004
K.Kurata, V.Breton, and H.Nakamura, "A Method to Verify Originality of Sequences Secretly on Distributed Computing Environment", Proceedings of HPCAsia2004, pp. 310-319, July, 2004
H.Nakamura, T.Hayashida, M.Kondo, Y.Tajima, M.Imai, T.Nanya: "Skewed checkpointing for tolerating multi-nodes failures," SRDS2004 (Oct. 2004)
M.Tsukisaka, M.Imai, T. Nanya: "Asynchronous Scan-Latch Controller for Low Area Overhead DFT," ICCD2004, pp.66-71(Oct.2004).
K.Kurata, V.Breton, and H.Nakamura, "Secret Sequence Comparison in Distributed Computing Environments by Interval Sampling", Proceedings of IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology , pp.198-205, Oct., 2004
H. Nakamura, T. Hayashida, M. Kondo, Y. Tajima, M. Imai, and T. Nanya, "Skewed Checkpointing for Tolerating Multi-Node Failures", Proceedings of IEEE SRDS '04, pp.116-125 , Oct. 2004
M. Kondo and H. Nakamura, "Dynamic Processor Throttling for Power Efficient Computations", PACS'04 (Workshop on Power-Aware Computer Systems) in conjunction with MICRO-37, 2004
近藤正章、中村宏、"ビット分割によるレジスタファイル削減手法" 情報処理学会研究報告2004-ARC-159(3), pp.13-18, 2004 (SWoPP2004)
田島裕也、林田卓朗、近藤正章、今井雅、中村宏、南谷崇、"多重故障を考慮した計算機クラスタ向けSkewed Checkpointingの検討" 信学技報DC2004-19(2004-07), pp.37-42, 2004 (SWoPP2004)
佐々木広、近藤正章、中村宏、"GALS型構成を用いたクラスタ化スーパースカラにおける低消費電力化の検討"、情報処理学会研究報告 2004-ARC-160、pp.65-70、2004 (DesignGaia)
小暮千賀明, 今井雅, 近藤正章, 中村宏, 南谷崇, "遅延変動を考慮したスタンダードセルライブラリの構築と評価" 電子情報通信学会技術研究報告, VLD2004-63, pp. 13-18, 2004 (DesignGaia)

H.Saito, H.Nakamura, M.Fujita, and T.Nanya, Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method", Proc. of ASP-DAC 2003, pp.197-202, Kita-kyushu, Jan, 2003.
E.Kim, H.Saito, J.Lee, D.Lee, H.Nakamura, and T.Nanya, "Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units", Proc. of ASP-DAC 2003, pp.816-819, Kita-kyushu, Jan, 2003.
Nattha Sretasereekul, Takashi Nanya, "Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits", IEICE Trans. Fundamentals, Vol.E86-A, No.4, pp.900-907, April, 2003
K.Kurata, V.Breton, C.Saguez, G.Dine, and H.Nakamura "A method to find unique PCR products on the European Data Grid", ハイパフォーマンスコンピューティングと計算科学シンポジウムHPCS2003, pp.13-20, Jan, 2003
高橋睦史、近藤正章、朴泰祐、高橋大介、中村宏、佐藤三久 "HPC向けオンチップメモリプロセッサアーキテクチャSCIMAのSMP化の検討と性能評価", ハイパフォーマンスコンピューティングと計算科学シンポジウムHPCS2003, pp.47-54, Jan, 2003
M.Kondo and H.Nakamura, "Reducing Memory System Energy by Software-Controlled On-Chip Memory", IEICE Trans. on Electronics, Vol.E86-C , No.4, 2003
今井雅, Metehan Ozcan, 南谷崇, "SDIモデルに基づく局所同期型非同期式VLSI設計方式", 情報処理学会論文誌, Vol.44, No.5, May, 2003
Metehan Ocan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, "Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits", Trans. of IPSJ, Vol.44, No.5, May, 2003
E. Kim, H. Saito, J.-G. Lee, H. Nakamura, D.-I. Lee and T. Nanya:"Synthesis of a single-dual-single wrapper for a generalized synchronous variable computation time arithmetic unit," in Proc. Of IWLS, pp.29-35 (May 2003)
H.Saito, E.Kim, N.Sretasereekul, M.Imai, H.Nakamura, T.Nanya: "Control signal sharing using data-path delay information at control data flow graph description," in Proc. ASYNC2003, pp.184-193 (May 2003)
E. Kim, H. Saito, J.-G. Lee, H. Nakamura, D.-I. Lee and T. Nanya:"Implementation of a generalized synchronous variable computation time arithmetic unit with a single-dual-single wrapper,"in Proc. Of ITC-CSCC2003, pp.1075-1078 (July 2003)
N.Sretasereekul, H.Saito, M.Imai, E.Kim, M.Ozcan, K.Thongnoo, H.Nakamura, T.Nanya: "A zero-time-overhead asynchronous four-phase controller," in Proc. ISCAS, Vol.5, pp.205-208 (Oct.2003)
H.Saito, E.Kim. M.Imai, N.Sretasereekul, H.Nakamura, T.Nanya: "Control signal sharing of asynchronous circuits using datapath delay information"," in Proc. ISCAS, Vol.5, pp.617-620 (Oct.2003)
M.Kondo, T.Hayashida, M.Imai, H.Nakamura, T.Nanya, A.Hori: "Evaluation of checkpointing mechanizm on SCore cluster system," in IEICE　Trans. on Inf. & Syst, Vol.E86-D, No.12, pp.2553-2562 (Dec., 2003)
N.Sretasereekul, H.Saito, E.Kim, M.Imai, M.Ozcan, H.Nakamura, T.Nanya:"Synthesis of serial local clock controllers for asynchronous circuit design," in IEICE Trans on Fundamentals, Vol.E86-A, No.12, pp.3028-3037 (Dec. 2003)
Wen Gao, Xinyu Liu, Lei Wang, T. Nayna: "A reconfigurable high availability, infrastructure in cluster for　Grid"," 2nd International Workshop on Grid and Cooperative Computing (Dec.2003)

Hiroshi Saito, Alex Kondratyev, Takashi Nanya : "Design of Asynchronous Controllers with Delay Insensitive Interface", Proc. ASP-DAC/VLSI Design 2002, pp.93-98, (Jan. 2002)
H.Nakamura, M.Kondo, T.Ohneda, M.Fujita, S.Chiba, M.Sato, T.Boku, "Architecture and Compiler Co-Optimization for High Performance Computing", International Workshop on Innovative Architecture, Hawaii (Jan. 2002)
M. Kondo, M. Fujita, H. Nakamura, "Software-Controlled On-Chip Memory for High-Performance and Low-Power Computing", HPCA-8 Work-in-progress Session (2002)
Metehan Ozcan, Masashi Imai, Takashi Nanya : "Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchrounous Data-Path Circuits" to appear in Proc. ASYNC2002(Apr. 2002)
Motokazu Ozawa, Hiroshi Nakamura, Takashi Nanya: "Cascade ALU Architecture: Preserving Performance Scalability with Power Consumption Suppressed", to appear in Proc. COOL Chips V (Apr. 2002)
奥山、セッタセリークン、齋藤、南谷、黒田："階層型CDFGによる非同期コントローラの合成", 情報処理学会論文誌, Vol.43, No.5, pp.1225-1234 （May 2002)
M. Kondo, M. Iwamoto, and H. Nakamura, "Cache Line Impact on 3D PDE Solvers", the 4th International Symposium on High Performance Computing (ISHPC 2002), Lecture Notes in Computer Science 2327, pp.301-309, May 2002.
Masaaki Kondo, Shinichi Tanaka, Motonobu Fujita, Hiroshi Nakamura "Reducing Memory System Energy in Data Intensive Computations by Software-Controlled On-Chip Memory", COLP02 (Workshop on Compilers and Operating Systems for Low Power) in conjunction with PACT02
H. Saito, H. Nakamura, M. Fujita, and T. Nanya. "Logic Optimization of Asynchronous Speed Independent Controllers by Using Transduction Method." In Proc. IEEE/ACM International Workshop on Logic and Synthesis(IWLS) pp.245--250, June 2002.
Nattha Sretasereekul, Y. Okuyama, H.Saito, M.Imai, and T. Nanya "Flexible Partitioning of CDFGs for Compact Asynchronous Controllers." In Proc, International Technical Conference on Circuits/Systems, Computers and Communications, pp.1724-1727, July, 2002
H. Saito, T. Ogawa, T. Sakunkonchak, M. Fujita, and T. Nanya. "An Equivalence Checking Methodology for Hardware Oriented C-based Specifications." In Proc. IEEE International High Level Design Validation and Test Workshop (HLDVT), pp.139--144, October 2002.
Taku Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, "Design And Evaluation Of High Performance Microprocessor With Reconfigurable On-Chip Memory", IEEE Asia-Pacific Conference on Circuits and Systems 2002, pp.211-216, Singapore, Dec. 2002
近藤正章、大根田拓、田中慎一、中村宏, "ソフトウェア可制御オンチップメモリを用いた低消費電力化の検討", 並列処理シンポジウム JSPP '2002, pp.285-288, 2002
D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara, "Characteristics of Support Vector Machines in Gene Expression Analysis", Genome Informatics 13, pp., Tokyo, December, 2002
K. Kurata, G.Dine, G.Saguez, and H. Nakamura, "Rapid Analysis of Specificity of PCR Product on the Whole Genome", Int'l Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA02), pp.246-252 Las Vegas, 2002
H.Nakamura, T.Arai, and M.Fujita, "Formal Verification of a Pipelined Processor with New Memory Hierarchy using a Commercial Model Checker", Proc. of IEEE PRDC'02 (Pacific Rim Dependable Computing), pp.321-324, Tsukuba, Dec. 2002
T.Hayashida, M.Kondo, M.Imai, H.Nakamura, T.Nanya, and A.Hori, "Analysis on Checkpointing Mechanism of SCore Cluster System", Fastabstract of IEEE PRDC'02 (Pacific Rim Dependable Computing), pp.1-2, Tsukuba, Dec. 2002
H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, A. Yakovlev, and T. Nanya. "Designs of Asynchronous Controllers with Delay Insensitive Interface." IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences, vol.E85-A, no.12, pp.2577-2585, December 2002

Motokazu Ozawa, Yoichiro Ueno, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: "A cascade ALU architecture for asynchronous superscalar processors" IEICE Trans. on Electronics, Vol.E84-C, No.2. (Feb. 2001)
Nattha Sretasereekul and Takashi Nanya:"Eliminating Isochronic-fork constraints in quasi-delay-insensitive circuits" Proc. ASP-DAC2001 (Jan. 2001)
H.Kagotani, T.Okamoto, T.Nanya:"Synthesis of Two-Phase Asynchronous Control Circuits from Pipeline Dependency Graphs" Proc. ASP-DAC2001 (Jan. 2001)
Motokazu Ozawa, Masashi Imai, Yoichiro Ueno, Hiroshi Nakamura, Takashi Nanya: "Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors" Proc. ASYNC2001 pp.162-172, (Mar. 2001)
近藤正章, 朴泰祐, 中村宏, "SCIMAにおける性能最適化手法の検討", 情報処理学会研究会論文誌HPS, Vol.42, No.SIG12(HPS4),pp. 37-48, (2001)
M. Fujita, H. Nakamura: "The Standard SpecC Language", Proc. of ISSS2001, pp. 81-86, (Oct. 2001)
N. Hosaka, K. Kurata, and H. Nakamura, "Comparison of Methods for Probe Design", Genome Informatics 12, pp.449-450, Tokyo, (Dec. 2001)

亀田、南谷：“パルス論理による非同期式データパス回路の構成”電子情報通信学会論文誌,Vol.J83-D-I, No.1, pp.1-8 (Jan, 2000)
中村宏, 近藤正章, 大河原英喜, 朴泰祐: “ハイパフォーマンスコンピューティング向けアーキテクチャSCIMA” 情報処理学会論文誌 Vol.41, No.SIG5(HPS1), pp.15-27, (2000)
Rafael Morizawa, Takashi Nanya: " A four-phase handshaking asynchronous controller specification style and its idle-phase optimization " Proc. International Conf. on Chip Design Automation, pp.439-447 (August, 2000).
Rafael Morizawa, Takashi Nanya:"A specification style of four-phase handshaking asynchronous controllers and the optimization of its return-to-zero phase" to appear in IEICE Trans. on Fundamentals of Electronics, Information and Communication, (Dec. 2000)
M.Tsukisaka, T.Nanya:"A testable design for asynchronous fine-grain pipeline circuits",to appear in Proc. of 7th Pacific Rim International Conference on Dependable CComputing, (Dec.2000)

A.Savva and T.Nanya:"A gracefully degrading massively parallel system using the BSPM and its evaluation", IEEE Trans. on Computers, Vol.48, No.1, pp.38-52 (Jan. 1999)
籠谷、岡本、南谷：”同期式回路スケジューリング法に基づいた非同期式回路設計のための依存性グラフ作成法”電子情報通信学会論文誌A, Vol.J82-A, No.2, pp.239-246 (Feb. 1999）
T.Nanya, A.Takamura, M.Kuwako, M.Imai, M.Ozawa, M.Ozcan, R.Morizawa, H.Nakamura:"Scalable-Delay-Insensitive Design: A high-performance approach to dependable asynchronous systems (Invited paper)", Proc. International Symp. on Future of Intellectual Integrated Electronics, pp.531-540, Sendai, Japan (March 1999)
今井、中村、南谷：”SDIモデルに基づいた非同期式パイプライン・データパスの論理合成”情報処理学会論文誌Vol.40, No.4, pp.1547-1556 (April 1999)
Y.Kameda, S.V.Polonsky, M.Maezawa, T.Nanya:"Self-timed parallel adders based on DI RSFQ primitives", IEEE Trans. on Applied Superconductivity, Vol.9, No.2, pp4040-4045 (June 1999).

E.P.Duarte Jr. and T.Nanya:"A hierarchical adaptive distributed system-level diagnosis algorithm" IEEE Trans. on Computers, Vol.47, No.1, pp.34-45 (Jan.1998)
M.Sahni and T.Nanya:"On the CSC property of signal transition graph specifications for asynchronous circuit design (Best Paper Award)" Proc. ASP-DAC , pp.183-189 (Feb.1998)
A.Takamura, M.Imai, M.Ozawa, I.Fukasaku, T.Fujii, M.Kuwako, Y.Ueno, T.Nanya:"TITAC-2: An asynchronous 32-bit microprocessor (Outstanding Design Award)" Proc. ASP-DAC, pp.319-320 (Feb. 1998)
Y.Kameda, S.Polonsky, M.Maezawa, T.Nanya:"Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic", Proc. ASYNC-98, pp.262-273 (March 1998)
Takashi Nanya:"Asynchronous microprocessor architecture and design (invited paper)", Proc. FED-PDI Joint Confrence on 21th-Century Electron Devices (FPC'98) (June 1998)
E.P.Duarte Jr., G.Mansfield, T.Nanya, S.Noguchi :"Improving the Dependability of Network Management Systems", International Journal of Network Management, Vol.8, No.4, pp.244-253 (July 1998).

トンタック、南谷：“Quasi-Delay-Insensitive論理回路の縮退故障テスト”電子情報通信学会論文誌, Vol.J80-D-I, No.2, pp1-9 (Feb. 1997)
S.B.Park, T.Nanya: "Synthesis of asynchronous circuits from signal transitiongraph specifications ", IEICE Trans. on Information and Systems , Vol.E80-D-I, No.3, pp.326-335 (March 1997)
B.R. Kishore and T.Nanya: "On concurrent error detection of asynchronous circuits using mixed-signal approach", IEICE Trans. on Information and Systems , Vol.E80-D-I, No.3, pp.351-361 (March 1997)
高村、桑子、南谷：“非同期式プロセッサTITAC-IIの論理設計における高速化手法”、電子情報通信学会論文誌, Vol.J80-D-I, No.3, pp.pp.189-196 (March 1997)
米田、柴山、南谷：“プロセス代数に基づく非同期式論理回路の検証”電子情報通信学会論文誌, Vol.J80-D-I, No.3, pp.207-217 (March 1997)
E.P.Duarte Jr., T.Nanya, G.Mansfield, S.Nogichi:"Non-Broadcast Network Fault -Monitoring Based on System-Level Diagnosis", Proc. 5th International Symp. on Integrated Network Management , pp.597-609 (May 1997)
M.Maezawa, I.Kurosawa, M.Aoyagi, H.Nakagawa, Y.Kameda, T.Nanya:"Rapid single -flux-quantum dual-rail logic for asynchronous circuits" IEEE Trans. on App lied Superconductivity, Vol.7, No.2, pp.2705-2708 ( June 1997)
B.R. Kishore, Y.Kameda, T.Nanya:"A mixed-signal approach for on-line testing of asynchronous circuits - a case study " Proc. 3rd IEEE International On-li ne Testing Workshop, pp.91-95 (July 1997)
T. Nanya, A. Takamura, M. Kuwako, M. Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y. Ueno, F. Okamoto, H. Fujimoto, O. Fujita, M. Yamashina, M. Fukuma :" TITAC-2: A 32-bit Scalable-Delay-Insensitive Microprocessor", Proc. of HOT C hips IX, pp.19-32 (Aug. 1997)
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno and Takashi Nanya:"TITAC-2: A 32-bit Asynch ronous Microprocessor based on Scalable-Delay-Insensitive Model" Proc. ICCD' 97, pp.288-294 (Oct.1997)

S.-B. Park and T.Nanya:"Automatic synthesis of speed-independent circuits f rom signal transition graph specifications", Proc. of 9th Int. Conf. on VLS I Design, pp.389-392 (Jan. 1996).
T.Nanya:"A new perspective on asynchronous VLSI system design", Proc. of 3rd Asia Pacific Conf. on Hardware Description Languages, pp.120-127 (Jan. 1996)
E.P.Duarte Jr., T.Nanya:"Application of distributed system-level diagnosis for SNMP-based internet fault management", Proc. 10th IEEE International Con ference on Information Networking (ICOIN-10) , pp.474-481 (Jan.1996) .
M.Maezawa, I.Kurosawa, Y.Kameda and T.Nanya:"Pulse-driven dual-rail logic gate family based on rapid single flux quantum(RSFQ) devices for asynchronous circuits", Proc. ASYNC'96, pp.134-142 (March 1996)
亀田、黒沢、南谷：“パルス駆動型非同期式回路の基本素子モデルと組合せ論理回路構成”電子情報通信学会論文誌, Vol.J79-D-I, No.3, pp.140-147 (March 1996)
E.P.Duarte Jr. and.T.Nanya:"An SNMP-based Implementation of the Adaptive Dis tributed System-level Diagnosis Alogorithm for LAN Fault Management" IEEE/IF IP 1996 Network Operations and Management Symposium (NOMS '96) (April 1996)
籠谷、小幡、岡本、南谷：“相互排他処理機能の依存性グラフ表現とその2相式非同期回路による実現”電子情報通信学会論文誌, Vol.J79-D-I, No.5, pp.237-244(May 1996)
T. Nanya and Y. Kameda: "Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices" Proc. 1996 IEEE International Conf. on Computer Design, pp.419-424 (Oct.1996).
E.P.Duarte Jr. and T.Nanya:"Hierarchical adaptive distributed system-level diagnosis applied for SNMP-based network fault management" Proc. 15th Inter. Symp. on Reliable Distributed Systems, pp.98-107 (Oct.1996).

籠谷、南谷：“２相式非同期回路の高速化”電子情報通信学会論文誌, Vol.J78-D-I, No.4, pp.416-423 (April 1995).
E.P.Duarte Jr., T.Nanya:"Distributed computing security through network mana gement systems", Proc. Middle East Info Tech, pp.179-192(May 1995)
S.Piestrak, T.Nanya:"Towards totally self-checking quasi-delay-insensitive systems", Proc. 25th Int. Symp.on Fault-Tolerant Computing, pp.228-237 (June 1995) .
A.Savva, T.Nanya:"Gracefully degrading systems using the bulk-synchronous pa rallel model with randomised shared memory", Proc. 25th Int. Symp.on Fault-T olerant Computing, pp.299-308 (June 1995) .
R.Takahashi, T.Nanya:"Multilevel Logic Design for Testability using Orthonor mal Expansions", Proc. Internatinal Workshop on Logic Synthesis, pp.641-646 (May 1995)
I.Kurosawa, H.Nakagawa, M.Aoyagi, M.Maezawa, Y.Kameda, T.Nanya:"A basic cir cuit for asynchronous superconductive logic using RSFQ gates", Proc. 5th Int .Superconductive Electronics Conf. , pp.204-206 (Sep. 1995)

T.Nanya: "Anti-code-disjoint mapping for exception handling in self-checking system hierarchy", Int. J. of Computer Systems Science and Engineering, Vol .9, No.1, pp.46-53 (Jan. 1994).
T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, A. Takamura: "TITAC: Design of a Quasi-Delay-Insensitive Microprocessor", IEEE Design & Test of Computers, Vo l.11, No.2, pp.50-63 (Summer 1994).
籠谷、南谷：“依存性グラフを用いた２相式非同期回路の合成”電子情報通信学会論文誌, Vol.J77-D-I, No.8, pp.548-556 (Aug. 1994)
S.-B.Park, T.Nanya:"A direct verification of CSC property of STG/FCs for asy nchronous circuit design", Proc. APCHDL'94 , pp.169-176 (Oct.1994) .
H.Kagotani, T.Nanya:"A synthesis method of quasi-delay-insensitive processor s based on dependency graph", Proc. APCHDL'94, pp.177-184 (Oct.1994).
M.Kuwako, T.Nanya:"Timing-reliability evaluation of asynchronous circuits ba sed on different delay models", Proc. ASYNC94, pp.22-31 (Nov.1994).
高橋、南谷：“正規直交展開を用いた論理回路のテスト容易性に関する一考察”電子情報通信学会論文誌、Vol.J77-D-1, No.12, pp.785-793 （Dec. 1994）

T.Nanya and M.Kuwako," On signal transition causality for self-timed implementation of combinational circuits", Proc. Hawaii Int.Conf.on System Science, pp.359-368 (Jan.1993).
丹、南谷：“フォールトトレランスを有する階層型ニューラルネットワークとその性質”電子情報通信学会論文誌, Vol.J76-D-I, No.7, pp.380-389 (July 1993)
Y.Tan and T.Nanya:"Fault-tolerant back-propagation model and its generalization ability", Proc. IJCNN, pp. 2516-2519 (Oct. 1993)
T.Nanya: "Anti-code-disjoint mapping for exception handling in self-checking system hierarchy", Proc. PRFTS'93, pp161-166 (Dec. 1993)

T.Nanya," Challenges to Asynchronous VLSI Processor Design", Proc. International Conference on Microelectronics, pp.III-1 - III-10 (Jan. 1992).
T.Nanya, S.Hatakenaka and R.Onoo,"Design of fully exercised SFS/SCD logic networks", FTCS-22, pp.96-103 (July 1992).
T.Nanya," Challenges to dependable asynchronous processor design", Proc. International Symp. on Logic Synthesis and Microprocessor Architecture, pp.132-139 (July 1992).
S.Hatakenaka and T.Nanya:"A design method of SFS and SCD combinational circuits", IEICE Trans. on Information and Systems, Vol.E75-D, No.6, pp.819-823 (Nov. 1992)

S.Hatakenaka and T.Nanya,"A design method of SFS and SCD combinational circuits", Proc. Pacific Rim Int.Symp. on Fault Tolerant Systems, pp.168-173 (Sep. 1991).

高原、南谷、：“CCS に基づく擬似非同期システムモデル”情報処理学会論文誌, Vol.30,No.1,pp.109-117 (Jan. 1989).
清水、南谷、：“交番検査方式による２線式検査回路の構成”、電子情報通信学会論文誌(D-I),Vol.J72-D-I,No.2,pp.126-132 (Feb. 1989)
T.Nanya and M.Uchida,"A strongly fault-secure and strongly code-disjoint realization of combinational circuits," FTCS-19, pp.390-397 (June 1989).
T.Nanya and M.Uchida,"The design of strongly fault-secure and strongly code-disjoint combinational circuits," '89 JFTCS, pp.245-250 (July 1989).
T.Nanya and H.A.Goosen,"The Byzantine hardware fault model", IEEE Trans. on CAD of Integrated Circuits and Systems,Vol.8,No.11, pp.1226-1231 (Nov. 1989).
南谷、内田：“分離符号を用いたセルフチェッキング組合せ回路の一構成法” 電子情報通信学会論文誌（D-I),Vol.J72-D-I,No.10,pp.902-910 (Dec. 1989).

T.Nanya and T.Kawamura,"Error secure/propagating concept and its application to the design of strongly fault secure processors," IEEE Trans.on Computers,Vol.37,No.1,pp.14-24 (Jan. 1988).
T.Nanya, S.Mourad and E.J.McCluskey,"Multiple stuck-at fault testability of self-testing checkers," FTCS-18, pp.381-386 (June 1988).
A.Takahara and T.Nanya,"A higher level hardware design verification" ICCD-88, pp.596-599 (Oct. 1988).

T.Nanya and T.Kawamura,"A note on strongly fault secure sequential circuits," IEEE Trans.on Computers,Vol.C-36,No.9,pp.1121-1123 (Sep. 1987).
T.Nanya and T.Kawamura,"On error indication for totally self-checking systems," IEEE Trans.on Computers,Vol.C-36,No.11,pp.1389-1392 (Nov.1987).
T.Nanya and H.A.Goosen,"Effect of Byzantine faults on concurrent error checking," ICCAD-87,pp.242-245 (Nov. 1987).

南谷、河村：“セルフチェッキング順序回路に関する一考察”、電子通信学会論文誌(D),Vol.J69-D,No.5,pp.701-705 (昭61-05, May 1986).
南谷、河村：“セルフチェッキング・システムの誤り表示について”、電子通信学会論文誌(D),Vol.J69-D,No.5,pp.826-828 (昭61-05, May 1986).
高原、南谷：“高水準設計検証の一方式”、情報処理学会論文誌、 Vol.27, No.8, p p.783-792 (昭61-08, Aug. 1986).

南谷、浜松：“ｍ-out-of-２ｍ符号の部分符号に対する自己検査性検査回路”電子通信学会論文誌(D), Vol.J68-D, No.3, pp.229-236 ( 昭60-03, Mar.1985)
T.Nanya and T.Kawamura,"Error secure/propagating concept and its application to the design of strongly fault secure processors," 15th Int.Symp.on Fault-Tolerant Computing, pp.396-401 (June 1985).
南谷、河村：“セルフチェッキング・システムにおける誤り安全性と誤り伝搬性の概念”、電子通信学会論文誌(D), Vol.J68-D, No.12, pp.2007-2014 ( 昭60-12, Dec.1985).
南谷、河村：“セルフチェッキング・プロセッサの一構成法（論文賞）”、電子通信学会論文誌(D), Vol.J68-D, No.12, pp.2015-2026 (昭60-12, Dec.1985).

T.Yamada and T.Nanya,"Stuck-at fault tests in the presence of undetectable bridging faults," IEEE Trans.on Computers, Vol.C-33, No.8, pp.758-761 (Aug. 1984).

T.Yamada and T.Nanya,"Comments on" detection and location of input and feedback bridging faults among input and output lines"," IEEE Trans. on Computers, Vol.C-32, No.5, pp.511-512 (May 1983).
T.Nanya and Y.Tohma,"A 3-level realization of totally self-checking checkers for M-out-of-N codes," 13th Int. Symp. on Fault-Tolerant Computing, pp.173-176 (June 1983).
南谷、当麻：“３段実現によるｍ-out-of-ｎ符号の自己検査性検査回路（手島記念研究論文賞）”、情報処理学会論文誌, Vol.24, No.4, pp.453-461 ( 昭58-07, July 1983).

山田、南谷：“検出不能な短絡故障の下での論理縮退故障のテスト”、電子通信学会論文誌(D),Vol.J64-D, No.6, pp.543-544 ( 昭56-06, June 1981).

T.Nanya and Y.Tohma,"Design of self-checking asynchronous sequential circuits," 10th Int.Symp.on Fault-Tolerant Computing, pp.278-280 (Oct. 1980).

T.Nanya and Y.Tohma,"Universal multicode STT state assignments for asynchronous sequential machines," IEEE Trans.on Computers, Vol.C-28, No.11, pp.811-818 (Nov. 1979).
南谷：“阿江、菅原、増山氏の「多資源非同期式アービタの一形式」に対する意見”、電子通信学会論文誌(D), Vol.J62-D, No.11, pp.775-777 (昭 54-11, Nov. 1979).

T.Nanya and Y.Tohma,"On universal single transition time asynchronous state assignments," IEEE Trans.on Computers, Vol.C-27, No.8,pp.781-782 (Aug. 1978).

南谷、古屋、石原、内藤：“中村、宇都宮両氏の「セミモジュラ非同期回路の汎用構成手順」に対する意見”、電子通信学会論文誌 (D),Vol.60-D,No.1,pp. 82-83 (昭52-01, Jan.1977).
南谷：“機能モジュールによる非同期式順序回路の合成”、電子通信学会論文誌(D), Vol.60-D, No.2, pp.135-142 (昭52-02, Feb.1977).
南谷：“非同期式順序回路の万能ＳＴＴ状態割当”、電子通信学会論文誌 (D), Vol.60-D, No.10, pp.846-853 ( 昭52-10, Oct.1977).

南谷、内藤：”正論理負論理併用による非同期式順序回路の一構成法”、電子通信学会論文誌(D), Vol.59-D, No.2, pp.125-126 (昭51-02, Feb.1976).

南谷：“非同期式順序回路における遅延の影響とそのハザードフリー構成”、電子通信学会論文誌(D), Vol.58-D, No.7, pp.413-420 (昭50-07, July 1975).
T.Nanya,"Effects of stray delays and hazard-free realization of asynchronous sequential circuits", Systems, Computers, Controls, Vol.6, No.4, pp.20-28 (1975))

南谷、小池：“非同期式アービタの一構成法”、電子通信学会論文誌(D), Vol.57-D, No.4, pp.242-244 (昭49-04, Apr.1974).

K.Ohmori,S.Naito,T.Nanya and K.Nezu,"An application of cellular logic for high speed decoding of minimum-redundancy codes," Proc.AFIPS Conf.,Vol.41,pp.345-351 (Dec.1972).

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