This research started from April 2010 as a joint research project funded by Semiconductor Technology Academic Research Center (STARC).
Multi-core processors are becoming more popular today and heading towards many-core processors as the technology continues to shrink. Future System-on-Chips (SoCs) are also said to adopt many-core architecture which is composed of many cores embedded with memory and accelerators on a chip. Although putting many cores on a chip sounds promising, they can have negative impacts on the overall performance or power consumption because of the increased latency and lack of communication bandwidth. Thus a new paradigm called Network-on-Chip (NoC), where each IP core is connected by not on-chip bus but routers using packet switching, has recently attracted attention in SoC design.
However, there are two major problems for the implementation of NoC-based many-core SoCs. First, the design optimization becomes much more difficult than before due to the large design space to explore. Second, the optimization is still insufficient in terms of the overall SoC architecture because they don't take the important characteristics of NoC into account.
This research aims to address these problems and realize NoC-based many-core SoCs that truly enjoys the improvement in circuit technology. To this end, we propose an "NoC-oriented design" that considers inter-chip core-to-core communication as a major constraint in terms of performance, power and implementation cost.