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Publications
Conference Publications
  • Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, and Koji Inoue, "A Flexible Hardware Barrier Mechanism for Many-Core Processors", 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015). Jan. 2015.
  • Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano,Mitaro Namiki, Masaaki Kondo, and Hiroshi Nakamura, "Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-grain Power Gating", International Symposium on System-on-Chip 2014, Oct. 2014.
  • Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, and Hiroshi Nakamura, "Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors", Design, Automation and Test in Europe Conference and Exhibition (DATE 2014), March 2014.
  • Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, and Hiroshi Nakamura, "Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors", 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014). pp.843-848, Jan. 2014.
  • Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, and Masaaki Kondo, "Cool Mega Array: a highly energy efficient reconfigurable accelerator", International Conference on Field-Programmable Technologies (FPT 2011), pp.1-8, Dec. 2011.
  • K. Usami, T. Hashida, S. Koyama, T. Yamamoto, D. Ikebuchi, H. Amano, M. Namiki, M. Kondo, and H. Nakamura, "Adaptive Power Gating for Function Units in a Microprocessor", 11th IEEE International Symposium on Quality Electronic Design (ISQED-2010), pp.29-37, Mar. 2010.
  • D. Ikebuchi, N. Seki, Y. Kojima, M. Kamata, L. Zhao, H. Amano, T. Shirai, S. Koyama, T. Hashida, Y. Umahashi, H. Masuda, K. Usami, S. Takeda, H. Nakamura, M. Namiki, M. Kondo, "Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating", IEEE Asian Solid-State Circuits Conference 2009 (A-SSCC 2009), pp.281-284, Nov. 2009.
  • Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura, "Cooperative Shared Resource Access Control for Low-Power Chip Multiprocessors", 14th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED-2009), pp.177-182, Aug. 2009.
  • K. Usami, T. Shirai, T. Hashida, H. Masuda, S. Takeda, M. Nakata, N. Seki, H. Amano, M. Namiki, M. Imai, M. Kondo and H. Nakamura, "Design and Implementation of Fine-grain Power Gating with Ground Bounce Suppression," The 22nd IEEE International Conference on VLSI Design, pp.381-386, Jan. 2009.
  • Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitustaka Nakata, Kimivoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo and Hiroshi Nakamura, "A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000", XXVI International Conference on Computer Design (ICCD-2008), pp.612-617, Oct. 2007.
  • Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, and Takashi Nanya, "Power Reduction of Chip Multi-Processors using Shared Resource Control Cooperating with DVFS", XXV International Conference on Computer Design (ICCD-2007), pp.615-622, Oct. 2007.
  • Hiroshi Sasaki, Masaaki Kondo, and Hiroshi. Nakamura, "An Intra-Task DVFS Technique based on Statistical Analysis of Hardware Events", International Conference on Computing Frontiers 2007 (CF 2007), pp.123-130, May 2007.
  • Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, and Takashi Nanya, "Task Scheduling under Performance Constrations for Reducing Energy Consumption of GALS Multi-Processor SoC", Design Automation and Test in Europe 2007 (DATE 2007), April 2007.
  • Hiroshi Sasaki, Masaaki Kondo, and Hiroshi. Nakamura, "Energy-Efficient Dynamic Instruction Scheduling Logic through Instruction Grouping", International Symposium on Low Power Electronics and Design 2006 (ISLPED 2006), pp.43-48, Oct. 2006.
  • Masaaki Kondo and Hiroshi Nakamura, "Small, Fast and Low-Power Register File by Bit-Partitioning", 11th International Symposium on High-Performance Computer Architecture (HPCA 2005), pp.40-49, Feb. 2005.
  • Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, and Takashi Nanya, "Skewed Checkpointing for Tolerating Multi-Node Failures", 23rd Symposium on Reliable and Distributed Systems (SRDS 2004), pp.116-125, Oct. 2004.
  • Taku Ohneda, Masaaki Kondo, Masashi Imai, and Hiroshi Nakamura, "Design and Evaluation of High Performance Microprocessor with Reconfigurable On-Chip Memory", 2002 Asia-Pacific Conference on Circuits and Systems (APCCAS 2002), pp.211-216, October 2002.
  • Masaaki Kondo, Mitsugu Iwamoto, and Hiroshi Nakamura, "Cache Line Impact on 3D PDP Solvers", 4th International Symposium on High Performance Computing (ISHPC 2002), LNCS 2327, pp.301-309, May 2002.
  • Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, and Taisuke Boku, "SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing", 2000 International Conference on Computer Design (ICCD 2000), pp.105-111, Oct. 2000.
  • Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku, and Shuichi Sakai, "SCIMA: A Novel Processor Architecture for High Performance Computing", HPC-Asia 2000, pp.355-360, May 2000.

Journal/Magazine Publications
  • Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo and Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface 3D NoC", IEEE Micro Magazine, Vol.33, Issue No.6, pp.6-15, Nov/Dec. 2013.
  • Son Truong Nguyen, Masaaki Kondo, Tomoya Hirao, and Koji Inoue, "A Prototype System for Many-core Architecture SMYLEref with FPGA Evaluation Boards", IEICE Transactions on Information and Systems, Vol.E96-D, No.8, pp.1645-1653, Aug. 2013.
  • Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki, "Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design", INVITED PAPER, IEICE Transactions on Electronics, Vol.E96-C, No.4, pp.404-412, April 2013.
  • Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, "Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips", IEEE Micro Magazine, Vol.31, Issue No.6, Dec. 2011.
  • Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano, "Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units", IPSJ Transactions on System LSI Design Methodology, Vol.4, pp.182-192, Aug. 2011.
  • Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, "Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping", IEEE Transactions on VLSI, Vol.17 Issue 6, pp. 848-852, June 2009. (Transactions Briefs)
  • Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya, "Design Method of High Performance and Low Power Functional Units Considering Delay Variations", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No. 12, pp.3519-3528, Dec. 2006.
  • Masaaki Kondo, Takuro Hayashida, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, and Atsushi Hori, "Evaluation of Checkpointing Mechanism on SCore Cluster System", IEICE Transactions on Information and Systems, Vol.E86-D, No.12, Dec. 2003.
  • Masaaki Kondo and Hiroshi Nakamura, "Reducing Memory System Energy by Software-Controlled On-Chip Memory", IEICE Transactions on Electronics, Vol.E86-C, No. 4, pp.550-588, April 2003.

Workshop Publications
  • Takefumi Miyoshi, Keigo Shima, Masaaki Kondo, Hidetsugu Irie, Hiroki Honda, and Tsutomu Yoshinaga, "FLAT: A GPU Programming Framework to Provide Embedded MPI", 5th Workshop on General Purpose Processing on Graphics Processing Units (GPGPU 2012), pp. 20-29, March 2012.
  • Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, and Masaaki Kondo, "SLD-1(Silent Large Datapath)F A Ultra Low Power Reconfigurable Accelerator", IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIV), April 2011.
  • Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Daiki Masuda, Kimiyoshi Usami, Tetsuya Sunata, Kazuki Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, and Masaaki Kondo, "Geyser-1 and Geyser-2: MIPS R3000 CPU Chips with Fine-grain Runtime Power Gating", IEEE Symposium on Low-Power and High-Speed Chips, (COOL Chips XIII), April 2010.
  • Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, and Hiroshi Nakamura, "Power-Performance Modeling of Heterogeneous Cluster-Based Web Servers", Energy Efficient Grids, Clouds and Clusters Workshop (E2GC2), Oct. 2009.
  • T. Komoda, H. Sasaki, M. Kondo, H. Nakamura, gCompiler Directed Fine Grain Power Gating for Leakage@Power Reduction in Microprocessor Functional Units", 7th Workshop on Optimizations for DSP and Embedded Systems (ODES-2009), Mar, 2009
  • Masaaki Kondo, Hiroshi Sasaki, and Hiroshi Nakamura, "Improving Fairness, Throughput and Energy-Efficiency on a Chip Multiprocessor through DVFS", Workshop on Design, Architecture and Simulation of Chip Multi-Processors 2006 (dasCMP 2006) , Dec. 2006.
  • Hiroshi Sasaki, Masaaki Kondo, and Hiroshi. Nakamura, "Dynamic Instruction Cascading on GALS Microprocessor", International Workshop on Power And Timing Modeling, Optimization and Simulation 2005 (PATMOS 2005), LNCS 3728, pp30-39, Sep. 2005.
  • Masaaki Kondo and Hiroshi Nakamura, "Dynamic Processor Throttling for Power Efficient Computations", Workshop on Power-Aware Computer Systems 2004 (PACS 2004), LNCS 3471, pp120-134, Dec. 2004.
  • Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, and Mitsuhisa Sato, "SCIMA-SMP: On-chip Memory Processor Architecture for SMP", 3rd workshop on Memory performance issues, ACM Electronic Edition, pp. 121-128, June 2004.
  • Motonobu Fujita, Masaaki Kondo, and Hiroshi Nakamura "Data Movement Optimization for Software-Contorlled On-Chip Memory", 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT 2004), pp.120-127, Feb. 2004.
  • Masaaki Kondo, Shinichi Tanaka, Motonobu Fujita, Hiroshi Nakamura "Reducing Memory System Energy in Data Intensive Computations by Software-Controlled On-Chip Memory", Workshop on Compilers and Operating Systems for Low Power, (COLP 2002), Sep. 2002.
  • Hiroshi Nakamura, Masaaki Kondo, and Taisuke Boku, "Software Controlled Reconfigurable On-Chip Memory for High Performance Computing", 2nd International Workshop on Intelligent Memory Systems, LNCS 2107, pp.15-32, 2000.