I. Referred Journal

 

1.     P.R. Panda, H. Nakamura, N. D. Dutt, A. Nicolau, gAugmenting Loop Tiling with Data Alignment for Improved Cache Performanceh, IEEE Transactions on Computers, Vol.48, No.2, pp.142-149, February, 1999

2.     S. Aoki, R. Burkhalter, K. Kanaya, T. Yoshie, T. Boku, H. Nakamura, Y. Yamashita, gPerformance of lattice QCD programs on CP-PACSh, Parallel Computing, Vol.25 (1999), pp.1243-1255, 1999 (Issues 10-11, September)

3.     K. Nakazawa, H. Nakamura, T. Boku, I. Nakata, Y. Yamashita, gCP-PACS :  A massively parallel processor at the University of Tsukubah, Parallel Computing, Vol.25 (1999), pp.1635-1661, 1999

4.     M.Ozawa, M.Imai, Y.Ueno, H.Nakamura, and T.N anya, gA Cascade ALU architecture for asynchronous super-scalar processorsh, IEICE Trans. on Electronics, pp.229-237, Vol.E84-C , No.2, 2001

5.     M.Kondo and H.Nakamura, gReducing Memory System Energy by Software-Controlled On-Chip Memoryh, IEICE Trans. on Electronics, Vol.E86-C , No.4, pp.580-588, 2003

6.     K.Kurata, V.Breton, and H.Nakamura gFinding Unique PCR Products on Distributed Databaseh, IPSJ Transaction on Advanced Computer Systems, Vol.44 No.@SIG6(ACS1),pp. 34-44, 2003

7.     M.Ozcan, M.Imai, H.Nakamura and T.Nanya gVerification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuitsh, IPSJ Journal, Vol.44,  No.5, pp. 1244-1253, 2003

8.     M.Kondo, T.Hayashida, M.Imai, H.Nakamura, T.Nanya, and A.Hori gEvaluation of Checkpointing Mechanism on SCore Cluster Systemh, IEICE Trans. on Inf. & Syst, Vol.E86-D, No.12, pp.2553-2562, 2003      

9.     N.Sretasereekul, H.Saito, E.Kim, M.Ozcan, M.Imai, H.Nakamura and T.Nanya gSynthesis of Serial Local Clock Controllers for Asynchronous Circuit Designh, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Special Issue on VLSI Design and CAD Al gorithms, Vol.E-86-A, No.12, pp. 3028-3037, 2003

10.  D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara, gMultidimensional Support Vector Machines for Visualization of Gene Expression Datah, Bioinfomatics, Vol.21, No. 4 pp.439-444, 2005

11.  N. Jacq, C. Blanchet, E. Cornillot, K. Kurata, H. Nakamura, T. Sylvestre, V. Breton, gGrid as a Bioinformatic Toolh, Parallel Computing, Vol.30, pp.1093-1107, 2004

12.  Daisuke Komura, Kunihiro Nishimura, Shumpei Ishikawa, Binaya, Panda, Jing Huang, Hiroshi Nakamura, Sigeo Ihara, Michitaka Hirose, Keith W. Jones and Hiroyuki Aburatani, gNoise reduction from genotyping microarrays using probe level informationh, In Silico Biology, Vol. 6, 0009, 2006
(on-line Journal: http://www.bioinfo.de/isb/index.html)

13.  D. Komura, F. Shen, S. Ishikawa, K. R. Fitch, W. Chen, G. Liu, S. Ihara, H. Nakamura, M. E. Hurles, J. Zhang, S. W. Scherer, K. W. Jones, M. H.Sha pero, J. Huang, C. Lee and H. Aburatani, gGenome-wide detection of human copy number variations using high density DNA oligonucleotide arrays,h Genome Research, Vol.16, pp. 1575-1584, 2006

14.  K.Watanabe, M.Imai, M.Kondo, H.Nakamura, T.Nanya, gA Design Method of High Performance and Low Power Functional Units Considering Delay Variationsh, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E-89-A, No.12, pp. 3519-3528, 2006

15.  H. Sasaki, M. Kondo, and H. Nakamura, gEnergy-Efficient Dynamic Instruc tion Scheduling Logic through Instruction Groupingh, IEEE Transactions on Very Large Scale Integration Systems, Page(s): 848-852, Vol.17, Issue 6, 2009

16.  48.   H. Matsutani, M. Koibuchi, D. Ikebuchi, K. Usami, H. Nakamura, and H Amano, "Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs", IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD), Vol.30, No.4, pp.520-533. Apr 2011

17.  Z.Lei, D.Ikebuchi, K.Usami, M.Namiki, M.Kondo, H.Nakamura, H.Amano, gDesign and Implementation of Fine-grained Power Gating on Processor Functional Unitsh IPSJ Trans. on System LSI Design Methodology, Vol.4, No.0, pp.182-192, 2011.

18.  S. Takeda, K. Kim, H. Nakamura, K. Usami, gSleep Transistor Sizing Method using Accurate Delay Estimation considering Input Vector Pattern and Non-Linear Current Modelh, IEICE Transaction Fundamentals of Electronics, Communications and Computer Sciences Vol.E94-A, No.12, pp. 2499-2509,  Dec. 2011

19.  Y. He, H. Sasaki, H. Matsutani, and H. Nakamura, gAdaptive Data Compression on 3D Network-on-Chips for CMPsh, IPSJ Trans. on ACS, Vol.5, No.1, 80-87 (2012-01-27)

20.  N. Ozaki, Y. Yasuda, M. Izawa, Y. Saito,  D. Ikebuchi, H. Amano, H. Nakamura, K. Usami, M.  Namiki, and M. Kondo, gCool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chipsh, IEEE MICRO Magazine, Vol.31, No.6, pp. 6-18, 2011

21.  K. Kim, S. Takeda, S. Miwa and H. Nakamura, gEvaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Cachesh, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E-95, No.12, pp.2301-2308, 2012

22.  H. Nakamura, W. Wang, Y. Ohta, K. Usami, H. Amano, M. Kondo, and M. Namiki,  gFine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Designh, IEICE Transactions on Electronics,  Vol.E96-C  No.4  pp.404-412, 2013 (Invited)D

23.  T. Nakada, K. Okamoto, T. Komoda, S. Miwa, Y. Sato, H. Ueki, M. Hayashikoshi, T. Shimizu, and H. Nakamura: Design Aid of Multi-core Embedded Systems with Energy Model, ī•ńˆ—Šw‰ļ˜_•¶Ž ƒRƒ“ƒsƒ…[ƒeƒBƒ“ƒOƒVƒXƒeƒ€iACSjCVol.7CNo.3Dpp.37-46C2014”N8ŒŽ

24.  S. Miwa, T. Inoue and H. Nakamura: Area-Efficient Microarchitecture for Reinforcement of Turbo Mode, IEICE Transactions on Information and Systems, Vol.E97-D, No.5, pp.1196-1210, 2014”N5ŒŽ

25.  A. Koshiba, M. Wada, R. Sakamoto, M. Sato, T. Kosaka, K. Usami, H. Amano, M. Kondo, H. Nakamura, and M. Namiki: A Fine-grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units, IEICE TRANSACTIONS on Electronics, Vol.E98-C, No.7, pp.559-568 (2015)

26.  Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura: A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip, IEICE Trans. on Information and Systems, Vol.E99-D, No.12, pp.2881--2890, Dec. (2016)

27.  Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki, An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Transactions 99-C(8): 926-935 (2016)

28.  Takashi NAKADA, Tomoki HATANAKA, Hiroshi UEKI, Masanori HAYASHIKOSHI, Toru SHIMIZU, and Hiroshi NAKAMURA, An Energy-Efficient Task Scheduling for Near-realtime Systems with Execution Time Variation: IEICE Trans. on Information and Systems, Vol.E100-D, No.10, pp.2493--2504, Oct. (2017)

29.  Shresthamali Shaswot, Masaaki Kondo, and Hiroshi Nakamura, "Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning," ACM Transactions on Embedded Computing Systems (TECS), Vol. 16, Issue 5s, Article No. 181, October 2017

 

 

II. Referred International Conference, Workshop

 

1.     H.Nakamura, M.Fujita, S.Kono, and H.Tanaka, gTemporal Logic Based Fast Verification System Using Cover Expressionsh, Proceedings of International Conference on Very Large Scale Integration '87 (IFIP), pp.99-111, August, 1987

2.     H.Nakamura, M.Fujita, S.Kono, M.Nakai, and H.Ta naka, gA Data Path Verification System using Temporal Logic Based Language: Tokioh, Proceedings of IFIP WG10.2 Working Conference on the CAD Systems Using AI Techniques (IFIP), pp.127-134, June, 1989

3.     H.Nakamura, Masaya Nakai, S.Kono, M.Fujita, and H.Tanaka, gLogic Design Assistance Using Temporal Logic Based Language Tokioh, Proceedings of Logic Programming Conference '89 (Lecture Note in Artificial Intelligence 485, Springer-Verlag),  pp.174-183, 1989

4.     H.Nakamura, Y.Kukimoto, M.Fujita, and H.Tanaka, gA Data Path Verifier For Register Transfer Level Using Temporal Logic Language Tokioh, Proceedings of Workshop on Computer-Aided Verification '90 (ACM/AMS), pp.493-504, 1990

5.     H.Nakamura, Y.Kukimoto, M.Fujita, and H.Tanaka, gPractical Design Assistance at Register Transfer Level using a Data Path Verifierh, Proceedings of International Conference on Computer Design '90 (IEEE), pp.99-102, Sept., 1990

6.     K.Nakazawa, H.Nakamura, H.Imori, and S.Kawabe, gPseudo Vector Processor based on Register-Windowed Superscalar Pipelineh, Proceedings of Supercomputing '92, pp.642-651, 1992

7.     H.Nakamura, M.Ito, H.Imori, and K.Nakazawa, gArch itecture and Implementation Description Language for Advanced Processor Designh, Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems '92, pp.213-218, Dec. 1992

8.     H.Nakamura, H.Imori, K.Nakazawa, T.Boku, I.Nakata, Y.Yamashita, H.Wada, and Y.Inagami, gA Scalar Architecture for Pseudo Vector P rocessing based on Slide-Windowed Registersh, Proceedings of ACM International Conference on Supercomputing '93, pp.298-307, July, 1993             

9.     H.Nakamura, K.Nakazawa, H.Li, H.Imori, T.Boku, I.Nakata, and Y.Yamashita, gEvaluation of Pseudo Vector Processor based on Slide-Windowed Registersh,  Proceedings of HICSS-27 (IEEE,ACM), pp.368-377, Jan, 1994

10.  H.Nakamura, T.Wakabayashi, K.Nakazawa, T.Boku, H.Wada, and Y.Ina gami, gPseudo Vector Processor for High-speed List Vector Computation with Hiding Memory Access Latencyh, Proceedings of IEEE TENCON '94, pp.338-342, August, 1994

11.  T.Morimoto, K.Yamazaki, H.Nakamura, T.Boku and K.Nakazawa, gSupe rscalar Processor Design with Hardware Description Language AIDLh, Proceedings of 2nd Asia-Pacific Conference on Hardware Description Languages, pp.51-58, Oct. 1994

12.  T.Morimoto, K.Saito, H.Nakamura, T.Boku, K.Nakazawa, gAdvanced Processor Design Using Hardware Description Language AIDLh, Asia and South Pacific Design Automation Conference (ASP-DAC'97), pp387-390, Makuhari, Japan, Jan. 1997,

13.  K.Itakura, T.Boku, H.Nakamura, K.Nakazawa, gPerformance evaluation of CP-PACS on CG benchmarkh, High Performance Computing Asia (HPC-Asia'97), pp.678-683, Seoul, Korea, May, 1997

14.  Y.Abei, K.Itakura, T.Boku, H.Nakamura, K.Nakazawa, gPerformance Imp rovement for Matrix Calculation on CP-PACS Node Processorh, High Performance Computing Asia (HPC-Asia'97), pp.672-677, Seoul, Korea, May, 1997

15.  Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau, gImproving Cache Performance through Tiling and Data Alignmenth, Solving Irregularly Structured Problems in Parallel, Lecture Notes in Computer Science, pp167-185, Vol 1253, Springer-Verlag, 1997 [Presented at the 4th International Symposium on Solving Irregularly Structured Problems in Parallel (IRREGULAR'97), Paderborn, June 1997]

16.  T.Boku, K.Itakura, H.Nakamura, and K.Nakazawa, gCP-PACS: A massively parallel processor for large scale scientific calculationsh, ACM International Conference on Supercomputing 97 (ICS'97), pp.108-115, Vienna, July 1997

17.  Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau, gA Data Alignment Technique for Improving Cache Performanceh, International Conference on Computer Design (ICCD-97), pp.587-592, Austin, October 1997

18.  H.Nakamura, K.Itakura, M.Matsubara, T.Boku, and K.Nakazawa, gEffectiveness of Register Preloading on CP-PACS Node Processorh, Proc. of Intern ational Workshop on Innovative Architecture (IWIA97), pp. 83-90, Maui, October 1997

19.  H.Nakamura, H. Okawara, M. Kondo, T. Boku, and S. Sakai, gSCIMA: A Novel Architecture for High Performance Computingh, Proc. of International Workshop on Innovative Architecture (IWIA99), pp. 45-53, Maui, October 1999

20.  M. Kondo, H. Okawara, H.Nakamura, T. Boku, and S. Sakai, gSCIMA: A Novel Processor Architecture for High Performance Computingh, High Performance Computing Asia (HPC-Asia '00), pp.355-360, Beijing, May 2000

21.  M. Kondo, H. Okawara, H.Nakamura, and T. Boku, gSCIMA: Software Controlled Integrated Memory Architecture for High Performance Computingh, Proc. of International Conference on Computer Design (ICCD-2000), pp.105-111, Austin, September 2000

22.  H.Nakamura, M.Kondo, and T.Boku, gSoftware Controlled Reconfigurable On-Chip Memory for High Performance Computingh, 2nd Workshop on Intelligent Memory Systems (IMS 2000), LNCS 2107, pp.15-32, November, 2000 (Springer-Verlag)

23.  K.Kurata and H.Nakamura, gNovel Method for Primer/Probe Design and Sequence Analysish, Genome Informatics, Vol.11, pp.331-332, Tokyo, December, 2000

24.  M.Ozawa, M.Imai, Y.Ueno, H.Nakamura, and T.Nanya, gPerformance Evaluation of Cascade ALU Architecture for Asynchronous Super-scalar Pipelineh, Proc. of ASYNC-2001, pp. 162-172, Utah, March, 2001

25.  M. Fujita, and H. Nakamura, gThe Standard SpecC Languageh, Proc. of  ISSS2001, pp. 81-86, October, 2001

26.  N. Hosaka, K. Kurata, and H. Nakamura, gComparison of Methods for Probe Designh, Genome Informatics, Vol.12, pp.449-450, Tokyo, December, 2001

27.  M. Kondo, M. Fujita, H. Nakamura, gSoftware-Controlled On-Chip Memory for High-Performance and Low-Power Computingh, HPCA-8 Work-in-progress Session, 2002, also in ACM SIG ARCH Computer Architecture News, Vol. 30, Issue 3, pp.7--8, ACM, 2002

28.  H.Nakamura, M.Kondo, T.Ohneda, M.Fujita, S.Chiba, M.Sato, T.Boku, g Architecture and Compiler Co-Optimization for High Performance Computingh, Proc. of International Workshop on Innovative Architecture (IWIA2002), pp. 50-56, Hawaii, January 2002

29.  M. Kondo, M. Iwamoto, and H. Nakamura, gCache Line Impact on 3D PDE Solversh, the 4th International Symposium on High Performance Computing (ISHPC 2002), Lecture Notes in Computer Science 2327, pp.301-309, May 2002.

30.  K. Kurata, G.Dine, G.Saguez, and H. Nakamura, gRapid Analysis of Specif icity of PCR Product on the Whole Genomeh, Intfl Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA02), pp.246-252 Las Vegas, 2002

31.  Taku Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, gDesign And Evaluation Of High Performance Microprocessor With Reconfigur able On-Chip Memoryh, IEEE Asia-Pacific Conference on Circuits and Systems 2002, pp.211-216, Singapore, Dec. 2002

32.  D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara, gCharacteristics of Support Vector Machines in Gene Expression Analysish, Genome Informatics, Vol.13, pp.264-265, Tokyo, December, 2002

33.  H.Nakamura, T.Arai, and M.Fujita, gFormal Verification of a Pipelined Processor with New Memory Hierarchy using a Commercial Model Checkerh, Proc. of IEEE PRDCf02 (Pacific Rim Dependable Computing), pp.321-324, Tsukuba, Dec. 2002

34.  H.Saito, H.Nakamura, M.Fujita, and T.Nanya, gLogic Optimization for Asynchronous Speed Independent Controllers Using Transduction Methodh, Proc. of ASP-DAC 2003, pp.197-202, Kita-kyushu, Jan, 2003.

35.  E.Kim, H.Saito, J.Lee, D.Lee, H.Nakamura, and T.Nanya, gPerformance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Unitsh, Proc. of ASP-DAC 2003, pp.816-819, Kita-kyushu, Jan, 2003.

36.  E.Kim, H.Saito, J.Lee, D.Lee, H.Nakamura, and T.Nanya, gDistributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Unitsh, Proc. DATE 03, pp. 276-281, Munich, 2003

37.  K.Kurata, V.Breton, and H.Nakamura gA method to find unique sequences on Distributed Genome Databaseh, Proc. of CCGrid 2003 (Cluster Computing and Grid), pp.62-69, Tokyo, May 2003

38.  H.Saito, E.Kim, M.Imai, N.Sretaserrekul, H.Nakamura, and T.Nanya, gControl Signal Sharing for Asynchronous Circuits Using Datapath Delay Informationh, Proc. of ISCAS 2003,  WAM2L-QP2.5, May, 2003

39.  N.Sretaserrekul, H.Saito, M.Imai, E.Kim, M.Ozcan, K.Thongnoo, H.Nak amura, and T.Nanya, gZero-Time-Overhead Asynchronous Four-Phase Controllerh, Proc. of ISCAS 2003, WAM2L-QP2.1, May, 2003

40.  H.Saito, E.Kim, M.Imai, N.Sretaserrekul, H.Nakamura, and T.Nanya, gControl Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptionsh, Proc. of Asynch 2003, pp. 184-195, May, 2003

41.  D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara. gFeatures of gene extraction by nonlinear support vector machines in gene expression analysish, Proceedings of Genome Informatics, Vol.14, pages 322-323, December 2003.

42.  M.Fujita, M. Kondo, and H. Nakamura gData Movement Optimization for Software-Controlled On-Chip Memoryh, Proc. of The 8th Workshop on Interac tion between Compilers and Computer Architectures (INTERACT-8) (in conjunction with HPCA04), pp.120-127, February, 2004

43.  D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara. gMultidimensional support vector machines for visualization of gene expression datah. Proceedings of ACM Symposium on Applied Computing, pp. 175-179, March 2004.

44.  C.Takahashi, M.Kondo, T.Boku, D.Takahashi, H.Nakamura, and M.Sato, gSCIMA-SMP: on-chip memory processor architecture for SMPh, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture (WMPI 04), ACM Electronic Edit ion, pp. 121-128, June 2004

45.  K.Kurata, V.Breton, and H.Nakamura, gA Method to Verify Original ity of Sequences Secretly on Distributed Computing Environmenth, Proceedings of HPCAsia2004, pp. 310-319, July, 2004

46.  K.Kurata, V.Breton, and H.Nakamura, gSecret Sequence Comparison in Distributed Computing Environments by Interval Samplingh, Proceedings of IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology , pp.198-205, Oct., 2004

47.  H. Nakamura, T. Hayashida, M. Kondo, Y. Tajima, M. Imai, and T. Nanya, gSkewed C heckpointing for Tolerating Multi-Node Failuresh, Proceedings of IEEE SRDS f04, pp.116-125 , Oct. 2004

48.  M. Kondo and H. Nakamura, gDynamic Processor Throttling for Power Efficient Computationsh, PACS2004 (Power-Aware Computer Systems), LNCS Vol.3471, pp. 120-134, Vol. 3471, 2005

49.  M. Kondo and H. Nakamura, gA Small, Fast and Low-Power Register File by Bit-Partitioningh, Proceedings of HPCA-11, pp.40-49, Feb. 2005

50.  H. Nakashima, H. Nakamura, M. Sato, T. Boku, S. Matsuoka, D. Takahashi, and Y. Hotta, gMegaProto: a low-power and compact cluster for high-performance computingh, Proc. of 19th International Parallel and Distributed Pro cessing Symposium (IPDPS-2005) HP-PAC Workshop (CD-ROM), April, 2005

51.  Ken-ichi  Kurata, Hiroshi Nakamura, Vincent Breton, gSecret Sequence Comparison on Public Grid Computing Resourcesh, Proceedings of CCGrid2005, pp.832-839, May, 2005

52.  H. Sasaki, M. Kondo, and H. Nakamura,  gDynamic Instruction Cas cading on GALS Microprocessorh, PATMOS2005, Lecture Notes in Computer Science, pp30-39, Vol 3728, Springer-Verlag, 2005

53.  H. Nakashima, H. Nakamura, M. Sato, T. Boku, S. Matsuoka, D. Takahashi, and Y. Hotta, gMegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technologyh, Proceedings of SC05, (CD-ROM), Nov. 2005

54.  T. Boku, M.Sato, D. Takahashi, H. Nakashima, H. Nakamura, S. Matsuoka, Y. Hotta, Y, gMegaProto/E: power-aware high-performance cluster with commodity technologyh, Proc. of 20th International Parallel and Distributed Pro cessing Symposium (IPDPS-2006) HP-PAC Workshop, (CD-ROM),  April, 2006

55.  H. Sasaki, M. Kondo, and H. Nakamura, gEnergy-Efficient Dynamic Instruc tion Scheduling Logic through Instruction Groupingh ISLPED-06, pp.43-48, Oct. 2006

56.  M. Kondo, H. Sasaki, and H. Nakamura, gImproving Fairness, Throughput and Energy Efficiency on a Chip Multiprocessor through DVFSh, International Workshop on Design, Architecture and Simulation of Chip Multi-Processors (DASCMP06 in conjunction with MICRO-39), Dec., 2006, (also in ACM SIGARCH Computer Architecture News, Vol. 35, No.1, pp.31-38, ACM, 2007)

57.  M. Kondo, Y. Ikeda, and H. Nakamura, gA High Performance Cluster System Design by Adaptive Power Controlh, Proc. of 21st International Parallel and Distributed Processing Symposium (IPDPS-2007) Workshop on High-Performance, Power-Aware Computing, (CD-ROM), March, 2007

58.  R. Watanabe, M. Kondo, M. Imai, H. Nakamura, T. Nayna, gTask Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoCh, Design Automation and Test in Europe (DATE07), pp. 797-802, April, 2007

59.  Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura, gAn Intra-Task DVFS Technique based on Statistical Analysis of Hardware Eventsh, Proc. of Computing Frontiers 2007, pp. 123-130, May, 2007

60.  R. Watanabe, M. Kondo, H. Nakamura, T. Nanya, gPower Reduction of Chip Multi-Processors using Shared Resource Control Cooperating with DVFSh, Proc. of International Conference on Computer Design (ICCD-2007), pp. 615-622, Lake Tahoe, Oct ober 2007

61.  T. Mishima, H. Nakamura, gA Proposal of New Dependable Database Middleware with Consistency and Concurrency Controlh, Proc. of IEEE PRDCf07 (Pacific Rim Dependable Computing), pp.334-337, Melbourne, Dec. 2007

62.  N. Seki, L. Zhao, J. Kei, D. Ikebuchi, Y. Kojima, Y. Hasegawa, H. Amano, T. Kashima, S. Takeda, T. Shirai, M. Nakata, K. Usami, T. Sunata, J. Kana i, M. Namiki, M. Kondo, and H. Nakamura, gA Fine Grain Dynamic Sleep Control S cheme in MIPS R3000h, Proc. of International Conference on Computer Design (ICCD-2008), pp. 612-617, Lake Tahoe, October 2008

63.  B. Nassu, T. Nanya, and H Nakamura, gDetecting Inconsistent Values caused by Interaction Faults Using Automatically Located Implicit Redundanciesh, Proc. of IEEE PRDCf08 (Pacific Rim Dependable Computing), pp. 138-145, Taipei, Dec. 2008

64.  B. Nassu, T. Nanya, and H Nakamura, gDiscovering Implicit Redundancies in Network Communications for Detecting Inconsistent Valuesh, Proc. of DDDM'08  (2nd International Workshop on Domain Driven Data Mining in conjunction with ICDMf08),Dec. 2008 (Data Mining Workshops, 2008. ICDMW '08. IEEE International Conference on, 15-19 Dec. 2008 Page(s):144 – 153)

65.  K.Usami, T.Shirai, T.Hashida, H.Masuda, S.Takeda, M.Nakata, N.Seki, H.Amano, M.Namiki, M.Imai, M.Kondo, and H.Nakamura, gDesign and Implementation of Fine-grain Power Gating with Ground Bounce Suppresionh, The 22nd IEEE International Conference on VLSI Design, pp. 381-386, India, Jan. 2009

66.  K.Usami, M.Nakata, T.Shirai, S.Takeda, N.Seki, H.Amano, and H.Nak amura, gImplementation and Evaluation of Fine-grain Run-time Power Gating for a Multiplierh, ICICDT (International Conference on IC Design and Technology), pp. 7-10, May 2009

67.  N.Takagi, H.Sasaki, M.Kondo, and H.Nakamura, gCooperative Shared Resource Access Control for Low Power Chip Multiprocessorsh, ISLPED-2009, pp. 177-182,  August, 2009 (CD-ROM)

68.  T.Mishima, and H.Nakamura, gPangea: An Eager Database Replication Middleware guaranteeing Snapshot Isolation without Modification of Database Serversh, VLDB09, pp.1066-1077 (CD-ROM), 2009

69.  H.Sasaki, T.Oya, M.Kondo and H.Nakamura, gPower-Performance Modeling of Heterogeneous Cluster-Based Web Serversh, E2GC2 (Energy Efficient Grids, Clouds and Clusters) workshop in conjunction with Grid2009, pp. 225-231, Oct., 2009

70.  D.Ikebuchi, N.Seki, Y.Kojima, M.Kamata, L.Zhao, H.Amano, T.Shirai,, S.Koyama, T.Hashida, Y.Umahashi, H.Masuda, K.Usami, S.Takeda, H.Nakamura, M.Namiki, M.Kondo, gGeyser-1: A MIPS R3000 CPU core with fine grain runtime power gatingh, Proc. of IEEE ASSCC (Asian Solid-State Circuits Conference), pp. 281-284, Nov., 2009

71.  K.Usami, T.Hashida, S.Koyama, T.Yamamoto, D.Ikebuchi,  H.Amano, M.Namiki, M.Kondo, H.Nakamura gAdaptive Power Gating for Function Units in a Microprocessorh, ISQED2010, pp. 29 - 37, March, 2010

72.  H. Matsutani, M. Koibuchi, D. Ikebuchi, K. Usami, H. Nakamura, H. Amano, "Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs", Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10), pp.61-68, May 2010

73.  68.   Y. Kodama, S. Itoh, T. Shimizu, S. Sekiguchi, H Nakamura and N. Mori, gPower Reduction Scheme of Fans in a Blade System by Considering the Imbalance of CPU Temperaturesh, The 2010 IEEE/ACM International Conference on Green Computing and Communications (GreenCom2010), pp. 81-87, Nov. 2010

74.  69.   L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo, gGeyser-2: The second prototype CPU with fine-grained run-time power gatingh, Proc. of IEEE ASP-DAC 2011, pp.87-88, 2011 (University Design Contest)

75.  70.   K. Usami, Y. Goto, K. Matsunaga, S. Koyama, D. Ikebuchi, H. Amano, H. Nakamura, gOn-chip detection methodology for break-even time of power gated function unitsh, Proc. of  ISLPED 2011pp. 241-246, 2011

76.  71.   N. Ozaki, Y. Yasuda, Y. Saito, D. Ikebuchi, M. Kimura, H. Amano, H. Nakamura, K. Usami, M. Namiki, M. Kondo: gCool Mega-Array: A highly energy efficient reconfigurable acceleratorh, Proc. of Field-Programmable Technology (FPT), 8pages, 2011

77.  H. Matsutani, Y. Hirata, M. Koibuchi, K. Usami , H. Nakamura, H. Amano, gA Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPsh, Proc. of IEEE ASP-DAC 2012, pp.407-412, 2012

78.  S. Takeda, S. Miwa, K. Usami, H. Nakamura, gEfficient Leakage Power Saving by Sleep Depth Controlling for Multi-mode Power Gatingh, Proc. of ISQED2012,  pp. 627-634, March, 2012

79.  S. Takeda, S. Miwa, K. Usami and H. Nakamura, "Stepwise Sleep Depth Control for Run-Time Leakage Power Saving", Proc. GLSVLSIf12 (Great Lakes Symposium on VLSI 2012), pp.233-238, May. 2012.

80.  K. Kim, S. Takeda, S. Miwa and H. Nakamura, "A Novel Power-Gating Scheme Utilizing Data Retentiveness on Caches", Proc. GLSVLSIf12 (Great Lakes Symposium on VLSI 2012), pp.91-94, May. 2012.

81.  T. Komoda, S. Miwa and H. Nakamura, "Communication Library to Overlap Computation and Communication for OpenCL Application", The 17th International Workshop on High-Level Parallel Programming Models and Supportive Environment (HIPS'12), pp.567-573, May. 2012. (in Conjunction with IEEE 26th IPDPS 2012)

82.  Y. Koizumi, E. Sasaki, H. Amano, H. Matsutani, Y. Take, T. Kuroda, R. Sakamoto,  M. Namiki, K. Usami, M. Kondo, and H. Nakamura, gCMA-CUBE: A SCALABLE RECONFIGURABLE ACCELERATOR WITH 3-D WIRELESS INDUCTIVE COUPLING INTERCONNECTh, Proc. of FPL 2012 (22nd International Conference on Field Programmable Logic and Applications), WP13, Aug. 2012 (poster)

83.  H. Sasaki, T. Tanimoto, K. Inoue, H. Nakamura, "Scalability-Based Manycore Partitioningh, Proc. of 21st PACT (The 22st International Conference on Parallel Architectures and Compilation Techniques),, pp107-116, Oct., 2012

84.  H. Noguchi, K. Nomura, K. Abe, S. Fujita, E. Arima, K. Kim, T. Nakada, S. Miwa and H. Nakamura: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM/MRAM Hybrid Memory, Design, Automation & Test in Europe (DATE'13), pp.1813-1818 , Mar. 2013

85.  Y. He, H. Sasaki, S. Miwa, and H. Nakamura, gPredict-more Router: A Low Latency NoC Router with More Route Predictionsh, The 3rd Workshop on Communication Architecture for Scalable Systems, pp.842-850, May. 2013. (in Conjunction with IEEE 27th IPDPS 2013)

86.  S. Miwa, S. Aita and H. Nakamura, gPerformance Estimation of High Performance Computing Systems with Energy Efficient Ethernet Technologyh, Proc. of International Conference on Energy-Aware High Performance Computing (EnA-HPC'13), 9pages, 2013 (DOI 10.1007/s00450-013-0238-4) at Springerlink.com

87.  Y. He, H. Sasaki, S. Miwa and H. Nakamura, gMcRouter: Multicast within a Router for High Performance Network-on-Chipsh, Proc. of 22nd PACT (The 22nd International Conference on Parallel Architectures and Compilation Techniques),  pp. 319-329, Sep. 2013

88.  T. Komoda, N. Maruyama, S. Miwa and H. Nakamura, gIntegrating Multi-GPU Execution in an OpenACC Compilerh, The 42nd International Conference on Parallel Processing (ICPP'13), 10 pages, Oct. 2013

89.  T. Nakada, S. Miwa, K. Yano and H. Nakamura, gPerformance Modeling for Designing NoC-based Multiprocessorsh, Proceedings of IEEE International Symposium on Rapid System Prototyping (RSP'13), pp.30—36, Oct. 2013

90.  T. Komoda, S. Hayashi, T. Nakada, S. Miwa and H. Nakamura, gPower Capping of CPU-GPU Heterogeneous Systems through Coordinating DVFS and Task Mappingh, Proceedings of IEEE 31st International Conference on Computer Design (ICCD'13), pp.349-356, (Oct. 2013)

91.  K. Usami, M. Kudo, K. Matsunaga, T. Kosaka, Y. Tsurui, W. Wang, H. Amano, H. Kobayashi, R. Sakamoto, M. Namik, M. Kondo, and H. Nakamura, gDesign and Control Methodology for Fine Grain Power Gating Based on Energy Characterization and Code Profiling of Microprocessorsh, Proc. of ASP-DAC 2014, pp.843-848, Jan. 2014

92.  M. Kondo, H. Kobayashi, R. Sakamoto, M. Wada, J. Tsukamoto, M. Namiki, W. Wang, H. Amano, K. Matsunaga, M. Kudo, K. Usami, T. Komoda and H. Nakamura, gDesign and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessorsh, Proc. of the 17th Design, Automation, and Test in Europe Conference (DATE'14), 6pages, (article no. 1485), Mar 2014.

93.  T. Nakada, T. Shigematsu, T. Komoda, S. Miwa, Y. Sato, H. Ueki, M. Hayashikoshi, T. Shimizu, and H. Nakamura: Data-aware Power Management for Periodic Real-time Systems with Non-Volatile Memory, The 3rd IEEE Nonvolatile Memory Systems and Applications Symposium (NVMSA'14), 6 pages, Aug. 2014

94.  K. Usami, M. Miyauchi, M. Kudo, K. Takagi, H. Amano, M. Namiki, M. Kondo, and H. Nakamura, gUnbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-grain Power Gatingh, SoC 2014 (International Symposium on System-on-Chip), 7pages, Oct. 2014 [Best Paper Award]

95.  E. Arima, H. Noguchi, T. Nakada, S. Miwa, S. Takeda, S. Fujita, H. Nakamura gImmediate Sleep: Reducing Energy Impact of Peripheral Circuits in STT-MRAM Caches," The 33rd IEEE International Conference on Computer Design (ICCD'15), pp. 157-164, Oct. (2015)

96.  Y. He, M. Kondo, T. Nakada, H. Sasaki, S. Miwa, H. Nakamura: "Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections," The 33rd IEEE International Conference on Computer Design (ICCD'15), pp.484-487, Oct. (2015)

97.  Susumu Takeda, Hiroki Noguchi, Kumiko Nomura, Shinobu Fujita, Shinobu Miwa, Eishi Arima, Takashi Nakada, Hiroshi Nakamura, "Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors", The 12th International SoC Design Conference (ISOCC), pp.153--154, Nov. (2015)

98.  S. Miwa, and H. Nakamura: Profile-based Power Shifting in Interconnection Networks with On/Off Links, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC'15), pp.37:1-37:11, Nov. 2015

99.  T. Nakada,  H. Yanagihashi,  H. Ueki,  T. Tsuchiya,  M. Hayashikoshi,  H. Nakamura, gEnergy-Efficient Continuous Task Scheduling for Near Real-time Periodic Tasksh, 8th IEEE International Conference on Internet of Things (iThings 2015), pp. 675-680, Dec. 2015

100.            Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita,Takashi Nakada, Hiroshi Nakamura, "4Mb STT-MRAM-based Cache with Memory-Access-aware Power Optimization and Novel Write-Verified-Write / Read-Modified-Write Scheme", 2016 IEEE International Conference of Solid-State Circuits (ISSCC), pp.132--133, Feb. (2016)

101.            Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura: "An Adaptive Energy-Efficient Task Scheduling under Execution Time Variation based on Statistical Analysis," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (poster), 7pages  Sep. (2016)

102.            Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano, The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. Proc. of MCSoC-17(IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip), Sep. (2017)

103.            Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura, Adaptive Power Management in Solar Energy Harvesting Sensor Node using Reinforcement Learning, Proc. of EMSOFT (2017)

104.            Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura: "Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6 pages, Oct. (2017) (Acceptance ratio=29%) (to appear)

105.            Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, and Mitaro Namiki, Building block multi-chip systems using inductive coupling Through Chip Interface, ISOCC2017, Seoul, Nov. 2017

106.            Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano, Scalable Deep Neural Network Accelerator Cores with Cubic Integration using Through Chip Interface, ISOCC2017, Seoul, Nov. 2017

  

III. Invited Talks, Tutorials

 

1.     H.Nakamura, gSystem and Architecture Level Approachesh, ASP-DACf06 Tutorial 3, Low Power / Low Leakage Technologies for Nanometer Era, Jan., 2006

2.     H. Nakamura, gPower Wall Problem: How to Make a Breakthrough? ~ Challenges and Opportunities for Architecture and Circuit-Level Co-Designh, ISVLSIf09 Keynote, May, 2009

3.     20.   H. Nakamura, gChallenges and Opportunities of Normally-Off Computingh, 13th International Forum on Embedded MPSoC and Multicore, Keynote 16/July, 2013

4.     21.   H. Nakamura, T. Nakada, S. Miwa, (Invited Paper) Normally-Off Computing Project : Challenges and Opportunities, The 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session 1S-1, pp.1--5, Jan. (2014)

5.     22.   H. Nakamura, gNormally-Off Computing for Sensor-Net Applicationsh, Forum F5: Low-Power Radios for Sensor Networks, ISSCC2014, Feb. 2014

6.     26.   H. Nakamura Short course on "Analog and Digital Circuit Design for IoT Swarmsg Symposium on VLSI Circuits 2015 (16, June)