発表文献リスト（中村宏）

I. 学位論文

Logic Design Assistance System based on Temporal Logic、東京大学、1990年3月、指導教官：田中英彦

II. 学術論文

1. 中村宏, 藤田昌宏,  河野真治,  田中英彦, “時相論理に基づく論理回路検証システム”, 情報処理学会論文誌 Vol.30, No.6, pp.771-778, 1989

2. 中村宏,  久木元裕治,  田中英彦, “時相論理を動作記述に用いたデータパス検証 システム”, 情報処理学会論文誌 Vol.31, No.8, pp.1251-1259, 1990

3. 中村宏,  位守弘充, 中澤喜三郎, “レジスタウィンドウ方式を用いた擬似ベクトルプロセッサの評価”, 情報処理学会論文誌 Vol.34, No.4, pp.669-680, 1993（論文賞受賞）

4. 位守弘充, 中村宏, 朴泰祐, 中澤喜三郎, “スライドウィンドウ方式による擬似ベクトルプロセッサ”, 情報処理学会論文誌 Vol.34, No.12, pp.2612-2623, 1993

5. 朴泰祐,  曽根猛, 三島健, 板倉憲一, 中澤喜三郎, 中村宏, “ハイパクロスバ網における適応ルーティングの導入とその評価”, 電子情報通信学会論文誌  Vol.J-78-D-I, No.2, pp.108-117, 1995

6. 朴泰祐,  曽根猛, 三島健, 板倉憲一, 中澤喜三郎, 中村宏, “ハイパクロスバ・ネットワークにおける転送性能向上のための手段とその評価”, 情報処理学会論文誌 Vol.36, No.7, pp.1610-1618, 1995

7. 曽根猛, 朴泰祐, 中村宏, 中澤喜三郎, “ハイパクロスバ・ネットワークにおけるVirtual Channelの動的選択による適応ルーティング”, 情報処理学会論文誌 Vol.37, No.7, pp.1409-1418, 1996

8. 廣野哲, 中村宏, 朴泰祐, 中澤喜三郎, “擬似ベクトルプロセッサにおける高速リストベクトル処理”, 情報処理学会論文誌 Vol.37, No.10, pp.1850-1857, 1996

9. 板倉憲一, 松原正純, 朴泰祐, 中村宏, 中澤喜三郎, “超並列計算機 CP-PACS におけるNPB Kernel CG の評価”, 情報処理学会論文誌 Vol.39, No.6, pp.1757-1765, 1998

10. P.R. Panda, H. Nakamura, N. D. Dutt, A. Nicolau, “Augmenting Loop Tiling with Data Alignment for Improved Cache Performance”, IEEE Transactions on Computers, Vol.48, No.2, pp.142-149, February, 1999

11. 今井雅, 中村宏, 南谷崇, “SDIモデルに基づいた非同期式パイプライン・データパスの論理合成”, 情報処理学会論文誌 Vol.40, No.4, pp.1947-1956, 1999

12. 三島健, 朴泰祐, 中村宏,　中澤喜三郎, “超並列計算機用多段結合網における転送性能の解析”, 情報処理学会論文誌 Vol.40, No.5, pp.1985-1995, 1999

13. S. Aoki, R. Burkhalter, K. Kanaya, T. Yoshie, T. Boku, H. Nakamura, Y. Yamashita, “Performance of lattice QCD programs on CP-PACS”, Parallel Computing, Vol.25 (1999), pp.1243-1255, 1999 (Issues 10-11, September)

14. K. Nakazawa, H. Nakamura, T. Boku, I. Nakata, Y. Yamashita, “CP-PACS :  A massively parallel processor at the University of Tsukuba”, Parallel Computing, Vol.25 (1999), pp.1635-1661, 1999

15. 中村宏, 大河原英喜, 近藤正章, 朴泰祐, “ハイパフォーマンスコンピューティング向けアーキテクチャSCIMA”, 情報処理学会論文誌ハイパフォーマンスコンピューティングシステム, Vol.41, No.SIG5(HPS1), pp.15-27, 2000

16. M.Ozawa, M.Imai, Y.Ueno, H.Nakamura, and T.Nanya, “A Cascade ALU arc hitecture for asynchronous super-scalar processors”, IEICE Trans. on Elect ronics, pp.229-237, Vol.E84-C , No.2, 2001

17. 近藤正章, 朴泰祐, 中村宏, “SCIMAにおける性能最適化手法の検討”, 情報処理学会論文誌ハイパフォーマンスコンピューティングシステム, Vol.42, No.SIG12(HPS4), pp. 37-48, 2001

18. M.Kondo and H.Nakamura, “Reducing Memory System Energy by Software-Controlled On-Chip Memory”, IEICE Trans. on Electronics, Vol.E86-C , No.4, pp.580-588, 2003

19. 高橋睦史, 近藤正章, 朴泰祐, 高橋大介, 中村宏, 佐藤三久, “HPC向けオンチップメモリプロセッサアーキテクチャSCIMAのSMP化の検討と性能評価”, 情報処理学会論文誌コンピューティングシステム, Vol.44 No.SIG6(ACS1), pp. 76-86, 2003

20. K.Kurata, V.Breton, and H.Nakamura “Finding Unique PCR Products on Dis tributed Database”, 情報処理学会論文誌コンピューティングシステム, Vol.44 No.　SIG6(ACS1),pp. 34-44, 2003

21. M.Ozcan, M.Imai, H.Nakamura and T.Nanya “Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits”, 情報処理学会論文誌, Vol.44,  No.5, pp. 1244-1253, 2003

22. M.Kondo, T.Hayashida, M.Imai, H.Nakamura, T.Nanya, and A.Hori “Evaluation of Checkpointing Mechanism on SCore Cluster System”, IEICE Trans. on Inf. & Syst, Vol.E86-D, No.12, pp.2553-2562, 2003      

23. 藤田元信, 近藤正章, 中村宏, “ソフトウェア制御オンチップメモリ向け自動最適化コンパイラの提案”, 情報処理学会論文誌コンピューティングシステム, Vol.45, No.SIG1(ACS4),pp. 77-87 (2004)

24. N.Sretasereekul, H.Saito, E.Kim, M.Ozcan, M.Imai, H.Nakamura and T.Nanya “Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Special Issue on VLSI Design and CAD Algorithms, Vol.E-86-A, No.12, pp. 3028-3037, 2003

25. 近藤正章, 中村宏, “主記憶アクセスの負荷情報を利用した動的周波数変更による低消費電力化”, 情報処理学会論文誌コンピューティングシステム, Vol.45, No.SIG6 (ACS6), pp. 1-11, 2004

26. 藤田元信, 田中慎一, 近藤正章, 中村宏, “ソフトウェア制御オンチップメモリにおけるスタティック消費電力削減手法”, 情報処理学会論文誌コンピューティングシステム, Vol.45, No.SIG11(ACS7), pp. 219-228, 2004

27. 堀田義彦, 佐藤三久, 朴泰祐, 高橋大介, 中島佳宏, 高橋睦史, 中村宏, “プロセッサの消費電力測定と低消費電力プロセッサによるクラスタの検討”, 情報処理学会論文誌コンピューティングシステム, Vol.45, No.SIG11(ACS7), pp. 207-218, 2004

28. D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara, “Multidimensional Support Vector Machines for Visualization of Gene Expression Data”, Bioinfomatics, Vol.21, No. 4 pp.439-444, 2005

29. N. Jacq, C. Blanchet, E. Cornillot, K. Kurata, H. Nakamura, T. Sylvestre, V. Breton^, “Grid as a Bioinformatic Tool”, Parallel Computing, Vol.30, pp.1093-1107, 2004

30. 中島浩, 中村宏, 佐藤三久, 朴泰祐, 松岡聡, 高橋大介, 堀田義彦, “高性能計算のための低電力・高密度クラスタMegaProto”, 情報処理学会論文誌コンピューティングシステム, Vol.46, No.SIG12(ACS11), pp. 46-61, 2005

31. 近藤正章, 中村宏, “ビット分割構成によるレジスタファイルのサイズおよびポート数削減手法”, 情報処理学会論文誌コンピューティングシステム, Vol.46, No.SIG12(ACS11), pp. 62-72, 2005

32. Daisuke Komura, Kunihiro Nishimura, Shumpei Ishikawa, Binaya, Panda, Jing Huang, Hiroshi Nakamura, Sigeo Ihara, Michitaka Hirose, Keith W. Jones and Hiroyuki Aburatani, “Noise reduction from genotyping microarrays using probe level information”, In Silico Biology, Vol. 6, 0009, 2006
(on-line Journal: http://www.bioinfo.de/isb/index.html)

33. 東美和子, 近藤正章, 今井雅, 中村宏, 南谷崇, “空間的に故障率が異なる計算機クラスタシステムにおけるチェックポインティング”, 電子情報通信学会論文誌分冊D, Vol.J89-D, No.8, pp1705-1716, 2006

34. 池田 佳路, 近藤 正章, 中村 宏, “実効電力制御による高性能計算機クラスタ構成手法の提案”, 情報処理学会論文誌コンピューティングシステム, Vol.47, No.SIG12 (ACS 15), pp.262-271, 2006

35. D. Komura, F. Shen, S. Ishikawa, K. R. Fitch, W. Chen, G. Liu, S. Ihara, H. Nakamura, M. E. Hurles, J. Zhang, S. W. Scherer, K. W. Jones, M. H.Sha pero, J. Huang, C. Lee and H. Aburatani, “Genome-wide detection of human copy number variations using high density DNA oligonucleotide arrays,” Genome Research, Vol.16, pp. 1575-1584, 2006

36. 佐々木 広, 浅井 雅司, 池田 佳路, 近藤 正章, 中村 宏, “統計処理に基づく動的電源電圧制御手法”, 情報処理学会論文誌コンピューティングシステム, Vol.47, No.SIG18 (ACS 16), pp.80-91, 2006

37. K.Watanabe, M.Imai, M.Kondo, H.Nakamura, T.Nanya, “A Design Method of High Performance and Low Power Functional Units Considering Delay Variations”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E-89-A, No.12, pp. 3519-3528, 2006

38. 近藤正章, 中村宏, “CMP向け動的電源電圧・周波数制御手法”, 情報処理学会論文誌コンピューティングシステム, 情報処理学会論文誌コンピューティングシステム, Vol.48, No.SIG13 (ACS 19), pp.260-269, 2007

39. 金井遵, 佐々木広, 近藤正章, 中村宏, 天野英晴, 宇佐美公良, 並木美太郎, “性能予測モデルの学習と実行時性能最適化機構を有する省電力化スケジューラ”, 情報処理学会論文誌コンピューティングシステム, Vol.49, No.SIG2 (ACS 21), pp.20-36, 2008

40. 大谷貴胤, 佐々木広, 近藤正章, 中村宏, “モデリングに基づくWebサーバ用計算機クラスタの低消費電力化”, 情報処理学会論文誌コンピューティングシステム, Vol.1, No.1, pp.120-132, 2008

41. 近藤正章, 佐々木広, 中村宏, “トラクションコントロール実行: CMP向けプロセス実行制御方式の提案”, 情報処理学会論文誌コンピューティングシステム, Vol.1, No.2, pp. 111-123, 2008

42. 高橋睦史，佐藤三久，高橋大介，朴泰祐，宇川彰，中村宏，青木秀貴，澤本 英雄，助川直伸，”演算加速機構を持つオンチップメモリプロセッサの検討と電力性能評価”, 情報処理学会論文誌コンピューティングシステム, Vol.2, No.1, pp. 158-172, 2009

43. H. Sasaki, M. Kondo, and H. Nakamura, “Energy-Efficient Dynamic Instruc tion Scheduling Logic through Instruction Grouping”, IEEE Transactions on Very Large Scale Integration Systems, Page(s): 848-852, Vol.17, Issue 6, 2009

44. 近藤正章, 高木紀子, 中村宏, “Pipeline Blocking: 走行時パワーゲーティングのための命令実行制御手法”, 情報処理学会論文誌コンピューティングシステム, Vol.2, No.3, pp. 83-95, 2009

45. 三島健, 中村宏, “eager レプリケーションミドルウェアの並行制御方法”, 電子情報通信学会論文誌分冊D, Vol.J93-D, No.3, pp.232-240, 2010

46. 関直臣, Lei Zhao, 小島　悠, 池淵 大輔, 長谷川 揚平, 大久保直昭, 武田清大, 香嶋俊裕, 白井利明, 宇佐美公良, 砂田徹也, 金井遵, 並木美太郎, 近藤 正章, 中村宏, 天野 英晴, MIPS R3000プロセッサにおける細粒度動的スリープ制御の実装と評価, 電子情報通信学会論文誌D, Vol.J93-D, No.6, pp.920-930, 2010 47. 松谷 宏紀, 鯉渕 道紘, 池淵 大輔, 宇佐美 公良, 中村 宏, 天野 英晴, "CMPにおけるオンチップルータの細粒度パワーゲーティングの評価", 情報処理学会論文誌コンピューティングシステム, Vol.3, No.3, pp.100-112, Sep 2010.

48. H. Matsutani, M. Koibuchi, D. Ikebuchi, K. Usami, H. Nakamura, and H Amano, "Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs", IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD), Vol.30, No.4, pp.520-533. Apr 2011

49. 吉田哲也，山田浩史，佐々木広，河野健二，中村宏，“マルチコア CPU の電力消費特性を考慮した仮想 CPU スケジューラ”，情報処理学会論文誌 コンピューティングシステム（ACS），Vol.4，No.2．pp.25-39，2011年3月．

50. 佐々木広，高木紀子，近藤正章，中村宏，“共有資源の競合を考慮したチップマルチプロセッサ向け低消費電力化手法”，情報処理学会論文誌 コンピューティングシステム（ACS），Vol.4，No.2．pp.40-58，2011年3月．

51. Z.Lei, D.Ikebuchi, K.Usami, M.Namiki, M.Kondo, H.Nakamura, H.Amano, “Design and Implementation of Fine-grained Power Gating on Processor Functional Units” IPSJ Trans. on System LSI Design Methodology, Vol.4, No.0, pp.182-192, 2011.

52. 薦田登志矢, 佐々木　広, 近藤正章, 中村宏, 細粒度な空き時間を利用したコンパイラによるリーク電力削減手法, 情報処理学会論文誌コンピューティングシステム(ACS), Vol.4, No.4, pp.36-50, 2011年10月.

53. S. Takeda, K. Kim, H. Nakamura, K. Usami, “Sleep Transistor Sizing Method using Accurate Delay Estimation considering Input Vector Pattern and Non-Linear Current Model”, IEICE Transaction Fundamentals of Electronics, Communications and Computer Sciences Vol.E94-A, No.12, pp. 2499-2509, Dec. 2011

54. Y. He, H. Sasaki, H. Matsutani, and H. Nakamura, “Adaptive Data Compression on 3D Network-on-Chips for CMPs”, IPSJ Trans. on ACS, Vol.5, No.1, 80-87 (2012-01-27)

55. N. Ozaki, Y. Yasuda, M. Izawa, Y. Saito, D. Ikebuchi, H. Amano, H. Nakamura, K. Usami, M. Namiki, and M. Kondo, “Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips”, IEEE MICRO Magazine, Vol.31, No.6, pp. 6-18, 2011

56. K. Kim, S. Takeda, S. Miwa and H. Nakamura, “Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E-95, No.12, pp.2301-2308, 2012

57. H. Nakamura, W. Wang, Y. Ohta, K. Usami, H. Amano, M. Kondo, and M. Namiki, “Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design”, IEICE Transactions on Electronics, Vol.E96-C No.4 pp.404-412, 2013 (Invited)

58. 有間 英志，薦田 登志矢，中田 尚，三輪 忍，中村 宏, “キャッシュ電源遮断時の性能ペナルティ削減のための損失データプリフェッチ”，情報処理学会論文誌 コンピューティングシステム（ACS），Vol.6，No.3．pp.118-130，2013年9月．

59. T. Nakada, K. Okamoto, T. Komoda, S. Miwa, Y. Sato, H. Ueki, M. Hayashikoshi, T. Shimizu, and H. Nakamura: Design Aid of Multi-core Embedded Systems with Energy Model, 情報処理学会論文誌 コンピューティングシステム（ACS），Vol.7，No.3．pp.37-46，2014年8月

60. S. Miwa, T. Inoue and H. Nakamura: Area-Efficient Microarchitecture for Reinforcement of Turbo Mode, IEICE Transactions on Information and Systems, Vol.E97-D, No.5, pp.1196-1210, 2014年5月

61. 有間 英志，薦田 登志矢，中田 尚，三輪 忍，野口 紘希，野村 久美子，安部 恵子，藤田 忍，中村 宏： 低CPU負荷を考慮したSTT-MRAMラスト・レベル・キャッシュの要求性能の解析， 電子情報通信学会論文誌，Vol.J97-A, No.10, pp.629-647, 2014年10月

62. 三輪 忍，會田 翔，安島 雄一郎，清水 俊幸，安里 彰，中村 宏： 実HPC環境におけるEEEの電力/性能評価， 情報処理学会論文誌 コンピューティングシステム(ACS)，Vol.7，No.4，pp.67-83 (2014-12-16)

63. A. Koshiba, M. Wada, R. Sakamoto, M. Sato, T. Kosaka, K. Usami, H. Amano, M. Kondo, H. Nakamura, and M. Namiki: A Fine-grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units, IEICE TRANSACTIONS on Electronics, Vol.E98-C, No.7, pp.559-568 (2015)

64. Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura: A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip, IEICE Trans. on Information and Systems, Vol.E99-D, No.12, pp.2881--2890, Dec. (2016)

65. Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki, An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Transactions 99-C(8): 926-935 (2016)

66. Takashi NAKADA, Tomoki HATANAKA, Hiroshi UEKI, Masanori HAYASHIKOSHI, Toru SHIMIZU, and Hiroshi NAKAMURA, An Energy-Efficient Task Scheduling for Near-realtime Systems with Execution Time Variation: IEICE Trans. on Information and Systems, Vol.E100-D, No.10, pp.2493--2504, Oct. (2017)

67. Shresthamali Shaswot, Masaaki Kondo, and Hiroshi Nakamura, "Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning," ACM Transactions on Embedded Computing Systems (TECS), Vol. 16, Issue 5s, Article No. 181, October 2017

III. 国際会議（査読つき）

1. H.Nakamura, M.Fujita, S.Kono, and H.Tanaka, “Temporal Logic Based Fast Verification System Using Cover Expressions”, Proceedings of International Conference on Very Large Scale Integration '87 (IFIP), pp.99-111, August, 1987

2. H.Nakamura, M.Fujita, S.Kono, M.Nakai, and H.Ta naka, “A Data Path Verification System using Temporal Logic Based Language: Tokio”, Proceedings of IFIP WG10.2 Working Conference on the CAD Systems Using AI Techniques (IFIP), pp.127-134, June, 1989

3. H.Nakamura, Masaya Nakai, S.Kono, M.Fujita, and H.Tanaka, “Logic Design Assistance Using Temporal Logic Based Language Tokio”, Proceedings of Logic Programming Conference '89 (Lecture Note in Artificial Intelligence 485, Springer-Verlag),  pp.174-183, 1989

4. H.Nakamura, Y.Kukimoto, M.Fujita, and H.Tanaka, “A Data Path Verifier For Register Transfer Level Using Temporal Logic Language Tokio”, Proceedings of Workshop on Computer-Aided Verification '90 (ACM/AMS), pp.493-504, 1990

5. H.Nakamura, Y.Kukimoto, M.Fujita, and H.Tanaka, “Practical Design Assistance at Register Transfer Level using a Data Path Verifier”, Proceedings of International Conference on Computer Design '90 (IEEE), pp.99-102, Sept., 1990

6. K.Nakazawa, H.Nakamura, H.Imori, and S.Kawabe, “Pseudo Vector Processor based on Register-Windowed Superscalar Pipeline”, Proceedings of Supercomputing '92, pp.642-651, 1992

7. H.Nakamura, M.Ito, H.Imori, and K.Nakazawa, “Arch itecture and Implementation Description Language for Advanced Processor Design”, Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems '92, pp.213-218, Dec. 1992

8. H.Nakamura, H.Imori, K.Nakazawa, T.Boku, I.Nakata, Y.Yamashita, H.Wada, and Y.Inagami, “A Scalar Architecture for Pseudo Vector P rocessing based on Slide-Windowed Registers”, Proceedings of ACM International Conference on Supercomputing '93, pp.298-307, July, 1993             

9. H.Nakamura, K.Nakazawa, H.Li, H.Imori, T.Boku, I.Nakata, and Y.Yamashita, “Evaluation of Pseudo Vector Processor based on Slide-Windowed Registers”,  Proceedings of HICSS-27 (IEEE,ACM), pp.368-377, Jan, 1994

10. H.Nakamura, T.Wakabayashi, K.Nakazawa, T.Boku, H.Wada, and Y.Ina gami, “Pseudo Vector Processor for High-speed List Vector Computation with Hiding Memory Access Latency”, Proceedings of IEEE TENCON '94, pp.338-342, August, 1994

11. T.Morimoto, K.Yamazaki, H.Nakamura, T.Boku and K.Nakazawa, “Supe rscalar Processor Design with Hardware Description Language AIDL”, Proceedings of 2nd Asia-Pacific Conference on Hardware Description Languages, pp.51-58, Oct. 1994

12. T.Morimoto, K.Saito, H.Nakamura, T.Boku, K.Nakazawa, “Advanced Processor Design Using Hardware Description Language AIDL”, Asia and South Pacific Design Automation Conference (ASP-DAC'97), pp387-390, Makuhari, Japan, Jan. 1997,

13. Y.Abei, K.Itakura, T.Boku, H.Nakamura, K.Nakazawa, “Performance Imp rovement for Matrix Calculation on CP-PACS Node Processor”, High Performance Computing Asia (HPC-Asia'97), pp.672-677, Seoul, Korea, May, 1997

14. K.Itakura, T.Boku, H.Nakamura, K.Nakazawa, “Performance evaluation of CP-PACS on CG benchmark”, High Performance Computing Asia (HPC-Asia'97), pp.678-683, Seoul, Korea, May, 1997

15. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau, “Improving Cache Performance through Tiling and Data Alignment”, Solving Irregularly Structured Problems in Parallel, Lecture Notes in Computer Science, pp167-185, Vol 1253, Springer-Verlag, 1997 [Presented at the 4th International Symposium on Solving Irregularly Structured Problems in Parallel (IRREGULAR'97), Paderborn, June 1997]

16. T.Boku, K.Itakura, H.Nakamura, and K.Nakazawa, “CP-PACS: A massively parallel processor for large scale scientific calculations”, ACM International Conference on Supercomputing 97 (ICS'97), pp.108-115, Vienna, July 1997

17. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau, “A Data Alignment Technique for Improving Cache Performance”, International Conference on Computer Design (ICCD-97), pp.587-592, Austin, October 1997

18. H.Nakamura, K.Itakura, M.Matsubara, T.Boku, and K.Nakazawa, “Effectiveness of Register Preloading on CP-PACS Node Processor”, Proc. of Intern ational Workshop on Innovative Architecture (IWIA97), pp. 83-90, Maui, October 1997

19. H.Nakamura, H. Okawara, M. Kondo, T. Boku, and S. Sakai, “SCIMA: A Novel Architecture for High Performance Computing”, Proc. of International Workshop on Innovative Architecture (IWIA99), pp. 45-53, Maui, October 1999

20. M. Kondo, H. Okawara, H.Nakamura, T. Boku, and S. Sakai, “SCIMA: A Novel Processor Architecture for High Performance Computing”, High Performance Computing Asia (HPC-Asia '00), pp.355-360, Beijing, May 2000

21. M. Kondo, H. Okawara, H.Nakamura, and T. Boku, “SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing”, Proc. of International Conference on Computer Design (ICCD-2000), pp.105-111, Austin, September 2000

22. H.Nakamura, M.Kondo, and T.Boku, “Software Controlled Reconfigurable On-Chip Memory for High Performance Computing”, 2nd Workshop on Intelligent Memory Systems (IMS 2000), LNCS 2107, pp.15-32, November, 2000 (Springer-Verlag)

23. M.Ozawa, M.Imai, Y.Ueno, H.Nakamura, and T.Nanya, “Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-scalar Pipeline”, Proc. of ASYNC-2001, pp. 162-172, Utah, March, 2001

24. M. Fujita, and H. Nakamura, “The Standard SpecC Language”, Proc. of  ISSS2001, pp. 81-86, October, 2001

25. H.Nakamura, M.Kondo, T.Ohneda, M.Fujita, S.Chiba, M.Sato, T.Boku, “ Architecture and Compiler Co-Optimization for High Performance Computing”, Proc. of International Workshop on Innovative Architecture (IWIA2002), pp. 50-56, Hawaii, January 2002

26. M. Kondo, M. Iwamoto, and H. Nakamura, “Cache Line Impact on 3D PDE Solvers”, the 4th International Symposium on High Performance Computing (ISHPC 2002), Lecture Notes in Computer Science 2327, pp.301-309, May 2002.

27. K. Kurata, G.Dine, G.Saguez, and H. Nakamura, “Rapid Analysis of Specif icity of PCR Product on the Whole Genome”, Int’l Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA02), pp.246-252 Las Vegas, 2002

28. Taku Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, “Design And Evaluation Of High Performance Microprocessor With Reconfigur able On-Chip Memory”, IEEE Asia-Pacific Conference on Circuits and Systems 2002, pp.211-216, Singapore, Dec. 2002

29. H.Nakamura, T.Arai, and M.Fujita, “Formal Verification of a Pipelined Processor with New Memory Hierarchy using a Commercial Model Checker”, Proc. of IEEE PRDC’02 (Pacific Rim Dependable Computing), pp.321-324, Tsukuba, Dec. 2002

30. H.Saito, H.Nakamura, M.Fujita, and T.Nanya, “Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method”, Proc. of ASP-DAC 2003, pp.197-202, Kita-kyushu, Jan, 2003.

31. E.Kim, H.Saito, J.Lee, D.Lee, H.Nakamura, and T.Nanya, “Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units”, Proc. of ASP-DAC 2003, pp.816-819, Kita-kyushu, Jan, 2003.

32. E.Kim, H.Saito, J.Lee, D.Lee, H.Nakamura, and T.Nanya, “Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units”, Proc. DATE 03, pp. 276-281, Munich, 2003

33. K.Kurata, V.Breton, and H.Nakamura “A method to find unique sequences on Distributed Genome Database”, Proc. of CCGrid 2003 (Cluster Computing and Grid), pp.62-69, Tokyo, May 2003

34. N.Sretaserrekul, H.Saito, M.Imai, E.Kim, M.Ozcan, K.Thongnoo, H.Nakamura, and T.Nanya, “Zero-Time-Overhead Asynchronous Four-Phase Controller”, Proc. of ISCAS 2003, pp.V-205 - V-208, May, 2003

35. H.Saito, E.Kim, M.Imai, N.Sretaserrekul, H.Nakamura, and T.Nanya, “Control Signal Sharing for Asynchronous Circuits Using Datapath Delay Information”, Proc. of ISCAS 2003, pp.V-617 - V-620, May, 2003

36. H.Saito, E.Kim, M.Imai, N.Sretaserrekul, H.Nakamura, and T.Nanya, “Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions”, Proc. of Asynch 2003, pp. 184-195, May, 2003

37. M.Fujita, M. Kondo, and H. Nakamura “Data Movement Optimization for Software-Controlled On-Chip Memory”, Proc. of The 8th Workshop on Interac tion between Compilers and Computer Architectures (INTERACT-8) (in conjunction with HPCA04), pp.120-127, February, 2004

38. D.Komura, H.Nakamura, S.Tsutsumi, H.Aburatani, and S.Ihara. “Multidimensional support vector machines for visualization of gene expression data”. Proceedings of ACM Symposium on Applied Computing, pp. 175-179, March 2004.

39. C.Takahashi, M.Kondo, T.Boku, D.Takahashi, H.Nakamura, and M.Sato, “SCIMA-SMP: on-chip memory processor architecture for SMP”, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture (WMPI 04), ACM Electronic Edit ion, pp. 121-128, June 2004

40. K.Kurata, V.Breton, and H.Nakamura, “A Method to Verify Original ity of Sequences Secretly on Distributed Computing Environment”, Proceedings of HPCAsia2004, pp. 310-319, July, 2004

41. K.Kurata, V.Breton, and H.Nakamura, “Secret Sequence Comparison in Distributed Computing Environments by Interval Sampling”, Proceedings of IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology , pp.198-205, Oct., 2004

42. H. Nakamura, T. Hayashida, M. Kondo, Y. Tajima, M. Imai, and T. Nanya, “Skewed C heckpointing for Tolerating Multi-Node Failures”, Proceedings of IEEE SRDS ’04, pp.116-125 , Oct. 2004

43. M. Kondo and H. Nakamura, “Dynamic Processor Throttling for Power Efficient Computations”, PACS2004 (Power-Aware Computer Systems), LNCS Vol.3471, pp. 120-134, Vol. 3471, 2005

44. M. Kondo and H. Nakamura, “A Small, Fast and Low-Power Register File by Bit-Partitioning”, Proceedings of HPCA-11, pp.40-49, Feb. 2005

45. H. Nakashima, H. Nakamura, M. Sato, T. Boku, S. Matsuoka, D. Takahashi, and Y. Hotta, “MegaProto: a low-power and compact cluster for high-performance computing”, Proc. of 19th International Parallel and Distributed Pro cessing Symposium (IPDPS-2005) HP-PAC Workshop (CD-ROM), April, 2005

46. Ken-ichi  Kurata, Hiroshi Nakamura, Vincent Breton, “Secret Sequence Comparison on Public Grid Computing Resources”, Proceedings of CCGrid2005, pp.832-839, May, 2005

47. H. Sasaki, M. Kondo, and H. Nakamura,  “Dynamic Instruction Cas cading on GALS Microprocessor”, PATMOS2005, Lecture Notes in Computer Science, pp30-39, Vol 3728, Springer-Verlag, 2005

48. H. Nakashima, H. Nakamura, M. Sato, T. Boku, S. Matsuoka, D. Takahashi, and Y. Hotta, “MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology”, Proceedings of SC05, (CD-ROM), Nov. 2005

49. T. Boku, M.Sato, D. Takahashi, H. Nakashima, H. Nakamura, S. Matsuoka, Y. Hotta, Y, “MegaProto/E: power-aware high-performance cluster with commodity technology”, Proc. of 20th International Parallel and Distributed Pro cessing Symposium (IPDPS-2006) HP-PAC Workshop, (CD-ROM),  April, 2006

50. H. Sasaki, M. Kondo, and H. Nakamura, “Energy-Efficient Dynamic Instruc tion Scheduling Logic through Instruction Grouping” ISLPED-06, pp.43-48, Oct. 2006

51. M. Kondo, H. Sasaki, and H. Nakamura, “Improving Fairness, Throughput and Energy Efficiency on a Chip Multiprocessor through DVFS”, International Workshop on Design, Architecture and Simulation of Chip Multi-Processors (DASCMP06 in conjunction with MICRO-39), Dec., 2006, (also in ACM SIGARCH Computer Architecture News, Vol. 35, No.1, pp.31-38, ACM, 2007)

52. M. Kondo, Y. Ikeda, and H. Nakamura, “A High Performance Cluster System Design by Adaptive Power Control”, Proc. of 21st International Parallel and Distributed Processing Symposium (IPDPS-2007) Workshop on High-Performance, Power-Aware Computing, (CD-ROM), March, 2007

53. R. Watanabe, M. Kondo, M. Imai, H. Nakamura, T. Nayna, “Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC”, Design Automation and Test in Europe (DATE07), pp. 797-802, April, 2007

54. Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura, “An Intra-Task DVFS Technique based on Statistical Analysis of Hardware Events”, Proc. of Computing Frontiers 2007, pp. 123-130, May, 2007

55. R. Watanabe, M. Kondo, H. Nakamura, T. Nanya, “Power Reduction of Chip Multi-Processors using Shared Resource Control Cooperating with DVFS”, Proc. of International Conference on Computer Design (ICCD-2007), pp. 615-622, Lake Tahoe, Oct ober 2007

56. T. Mishima, H. Nakamura, “A Proposal of New Dependable Database Middleware with Consistency and Concurrency Control”, Proc. of IEEE PRDC’07 (Pacific Rim Dependable Computing), pp.334-337, Melbourne, Dec. 2007

57. N. Seki, L. Zhao, J. Kei, D. Ikebuchi, Y. Kojima, Y. Hasegawa, H. Amano, T. Kashima, S. Takeda, T. Shirai, M. Nakata, K. Usami, T. Sunata, J. Kana i, M. Namiki, M. Kondo, and H. Nakamura, “A Fine Grain Dynamic Sleep Control S cheme in MIPS R3000”, Proc. of International Conference on Computer Design (ICCD-2008), pp. 612-617, Lake Tahoe, October 2008

58. B. Nassu, T. Nanya, and H Nakamura, “Detecting Inconsistent Values caused by Interaction Faults Using Automatically Located Implicit Redundancies”, Proc. of IEEE PRDC’08 (Pacific Rim Dependable Computing), pp. 138-145, Taipei, Dec. 2008

59. B. Nassu, T. Nanya, and H Nakamura, “Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values”, Proc. of IEEE International Conference on Data Mining Workshops (ICDMW), pp.144-153, Dec. 2008

60. K.Usami, T.Shirai, T.Hashida, H.Masuda, S.Takeda, M.Nakata, N.Seki, H.Amano, M.Namiki, M.Imai, M.Kondo, and H.Nakamura, “Design and Implementation of Fine-grain Power Gating with Ground Bounce Suppression”, The 22nd IEEE International Conference on VLSI Design, pp. 381-386, India, Jan. 2009

61. K.Usami, M.Nakata, T.Shirai, S.Takeda, N.Seki, H.Amano, and H.Nak amura, “Implementation and Evaluation of Fine-grain Run-time Power Gating for a Multiplier”, ICICDT (International Conference on IC Design and Technology), pp. 7-10, May 2009

62. N.Takagi, H.Sasaki, M.Kondo, and H.Nakamura, “Cooperative Shared Resource Access Control for Low Power Chip Multiprocessors”, ISLPED-2009, pp. 177-182,  August, 2009 (CD-ROM)

63. T.Mishima, and H.Nakamura, “Pangea: An Eager Database Replication Middleware guaranteeing Snapshot Isolation without Modification of Database Servers”, VLDB09, pp.1066-1077 (CD-ROM), 2009

64. H.Sasaki, T.Oya, M.Kondo and H.Nakamura, “Power-Performance Modeling of Heterogeneous Cluster-Based Web Servers”, E2GC2 (Energy Efficient Grids, Clouds and Clusters) workshop in conjunction with Grid2009, pp. 225-231, Oct., 2009

65. D.Ikebuchi, N.Seki, Y.Kojima, M.Kamata, L.Zhao, H.Amano, T.Shirai,, S.Koyama, T.Hashida, Y.Umahashi, H.Masuda, K.Usami, S.Takeda, H.Nakamura, M.Namiki, M.Kondo, “Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating”, Proc. of IEEE ASSCC (Asian Solid-State Circuits Conference), pp. 281-284, Nov., 2009

66. K.Usami, T.Hashida, S.Koyama, T.Yamamoto, D.Ikebuchi,  H.Amano, M.Namiki, M.Kondo, H.Nakamura “Adaptive Power Gating for Function Units in a Microprocessor”, ISQED2010, pp. 29 - 37, March, 2010

67. H. Matsutani, M. Koibuchi, D. Ikebuchi, K. Usami, H. Nakamura, H. Amano, "Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs", Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10), pp.61-68, May 2010

68. Y. Kodama, S. Itoh, T. Shimizu, S. Sekiguchi, H Nakamura and N. Mori, “Power Reduction Scheme of Fans in a Blade System by Considering the Imbalance of CPU Temperatures”, The 2010 IEEE/ACM International Conference on Green Computing and Communications (GreenCom2010), pp. 81-87, Nov. 2010

69. L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo, “Geyser-2: The second prototype CPU with fine-grained run-time power gating”, Proc. of IEEE ASP-DAC 2011, pp.87-88, 2011 (University Design Contest)

70. K. Usami, Y. Goto, K. Matsunaga, S. Koyama, D. Ikebuchi, H. Amano, H. Nakamura, “On-chip detection methodology for break-even time of power gated function units”, Proc. of ISLPED 2011pp. 241-246, 2011

71. N. Ozaki, Y. Yasuda, Y. Saito, D. Ikebuchi, M. Kimura, H. Amano, H. Nakamura, K. Usami, M. Namiki, M. Kondo: “Cool Mega-Array: A highly energy efficient reconfigurable accelerator”, Proc. of Field-Programmable Technology (FPT), 8pages, 2011

72. H. Matsutani, Y. Hirata, M. Koibuchi, K. Usami , H. Nakamura, H. Amano, “A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs”, Proc. of IEEE ASP-DAC 2012, pp.407-412, 2012

73. S. Takeda, S. Miwa, K. Usami, H. Nakamura, “Efficient Leakage Power Saving by Sleep Depth Controlling for Multi-mode Power Gating”, Proc. of ISQED2012, pp. 627-634, March, 2012

74. S. Takeda, S. Miwa, K. Usami and H. Nakamura, "Stepwise Sleep Depth Control for Run-Time Leakage Power Saving", Proc. GLSVLSI’12 (Great Lakes Symposium on VLSI 2012), pp.233-238, May. 2012.

75. K. Kim, S. Takeda, S. Miwa and H. Nakamura, "A Novel Power-Gating Scheme Utilizing Data Retentiveness on Caches", Proc. GLSVLSI’12 (Great Lakes Symposium on VLSI 2012), pp.91-94, May. 2012.

76. T. Komoda, S. Miwa and H. Nakamura, "Communication Library to Overlap Computation and Communication for OpenCL Application", The 17th International Workshop on High-Level Parallel Programming Models and Supportive Environment (HIPS'12), pp.567-573, May. 2012. (in Conjunction with IEEE 26th IPDPS 2012)

77. Y. Koizumi, E. Sasaki, H. Amano, H. Matsutani, Y. Take, T. Kuroda, R. Sakamoto, M. Namiki, K. Usami, M. Kondo, and H. Nakamura, “CMA-CUBE: A SCALABLE RECONFIGURABLE ACCELERATOR WITH 3-D WIRELESS INDUCTIVE COUPLING INTERCONNECT”, Proc. of FPL 2012 (22nd International Conference on Field Programmable Logic and Applications), WP13, Aug. 2012 (poster)

78. H. Sasaki, T. Tanimoto, K. Inoue, H. Nakamura, "Scalability-Based Manycore Partitioning”, Proc. of 21st PACT (The 22st International Conference on Parallel Architectures and Compilation Techniques),, pp107-116, Oct., 2012

79. H. Noguchi, K. Nomura, K. Abe, S. Fujita, E. Arima, K. Kim, T. Nakada, S. Miwa and H. Nakamura: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM/MRAM Hybrid Memory, Design, Automation & Test in Europe (DATE'13), pp.1813-1818 , Mar. 2013

80. Y. He, H. Sasaki, S. Miwa, and H. Nakamura, “Predict-more Router: A Low Latency NoC Router with More Route Predictions”, The 3rd Workshop on Communication Architecture for Scalable Systems, pp.842-850, May. 2013. (in Conjunction with IEEE 27th IPDPS 2013)

81. S. Miwa, S. Aita and H. Nakamura, “Performance Estimation of High Performance Computing Systems with Energy Efficient Ethernet Technology”, Proc. of International Conference on Energy-Aware High Performance Computing (EnA-HPC'13), 9pages, 2013 (DOI 10.1007/s00450-013-0238-4) at Springerlink.com

82. Y. He, H. Sasaki, S. Miwa and H. Nakamura, “McRouter: Multicast within a Router for High Performance Network-on-Chips”, Proc. of 22nd PACT (The 22nd International Conference on Parallel Architectures and Compilation Techniques), pp. 319-329, Sep. 2013

83. T. Komoda, N. Maruyama, S. Miwa and H. Nakamura, “Integrating Multi-GPU Execution in an OpenACC Compiler”, The 42nd International Conference on Parallel Processing (ICPP'13), 10 pages, Oct. 2013

84. T. Nakada, S. Miwa, K. Yano and H. Nakamura, “Performance Modeling for Designing NoC-based Multiprocessors”, Proceedings of IEEE International Symposium on Rapid System Prototyping (RSP'13), pp.30—36, Oct. 2013

85. T. Komoda, S. Hayashi, T. Nakada, S. Miwa and H. Nakamura, “Power Capping of CPU-GPU Heterogeneous Systems through Coordinating DVFS and Task Mapping”, Proceedings of IEEE 31st International Conference on Computer Design (ICCD'13), pp.349-356, (Oct. 2013)

86. K. Usami, M. Kudo, K. Matsunaga, T. Kosaka, Y. Tsurui, W. Wang, H. Amano, H. Kobayashi, R. Sakamoto, M. Namik, M. Kondo, and H. Nakamura, “Design and Control Methodology for Fine Grain Power Gating Based on Energy Characterization and Code Profiling of Microprocessors”, Proc. of ASP-DAC 2014, pp.843-848, Jan. 2014

87. M. Kondo, H. Kobayashi, R. Sakamoto, M. Wada, J. Tsukamoto, M. Namiki, W. Wang, H. Amano, K. Matsunaga, M. Kudo, K. Usami, T. Komoda and H. Nakamura, “Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors”, Proc. of the 17th Design, Automation, and Test in Europe Conference (DATE'14), 6pages, (article no. 1485), Mar 2014.

88. T. Nakada, T. Shigematsu, T. Komoda, S. Miwa, Y. Sato, H. Ueki, M. Hayashikoshi, T. Shimizu, and H. Nakamura: Data-aware Power Management for Periodic Real-time Systems with Non-Volatile Memory, The 3rd IEEE Nonvolatile Memory Systems and Applications Symposium (NVMSA'14), 6 pages, Aug. 2014

89. K. Usami, M. Miyauchi, M. Kudo, K. Takagi, H. Amano, M. Namiki, M. Kondo, and H. Nakamura, “Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-grain Power Gating”, SoC 2014 (International Symposium on System-on-Chip), 7pages, Oct. 2014 [Best Paper Award]

90. E. Arima, H. Noguchi, T. Nakada, S. Miwa, S. Takeda, S. Fujita, H. Nakamura “Immediate Sleep: Reducing Energy Impact of Peripheral Circuits in STT-MRAM Caches," The 33rd IEEE International Conference on Computer Design (ICCD'15), pp. 157-164, Oct. (2015)

91. Y. He, M. Kondo, T. Nakada, H. Sasaki, S. Miwa, H. Nakamura: "Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections," The 33rd IEEE International Conference on Computer Design (ICCD'15), pp.484-487, Oct. (2015)

92. Susumu Takeda, Hiroki Noguchi, Kumiko Nomura, Shinobu Fujita, Shinobu Miwa, Eishi Arima, Takashi Nakada, Hiroshi Nakamura, "Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors", The 12th International SoC Design Conference (ISOCC), pp.153--154, Nov. (2015)

93. S. Miwa, and H. Nakamura: Profile-based Power Shifting in Interconnection Networks with On/Off Links, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC'15), pp.37:1-37:11, Nov. 2015

94. T. Nakada, H. Yanagihashi, H. Ueki, T. Tsuchiya, M. Hayashikoshi, H. Nakamura, “Energy-Efficient Continuous Task Scheduling for Near Real-time Periodic Tasks”, 8th IEEE International Conference on Internet of Things (iThings 2015), pp. 675-680, Dec. 2015

95. Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita,Takashi Nakada, Hiroshi Nakamura, "4Mb STT-MRAM-based Cache with Memory-Access-aware Power Optimization and Novel Write-Verified-Write / Read-Modified-Write Scheme", 2016 IEEE International Conference of Solid-State Circuits (ISSCC), pp.132--133, Feb. (2016)

96. Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura: "An Adaptive Energy-Efficient Task Scheduling under Execution Time Variation based on Statistical Analysis," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (poster), 7pages Sep. (2016)

97. Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano, The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. Proc. of MCSoC-17(IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip), Sep. (2017)

Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura, Adaptive Power Management in Solar Energy Harvesting Sensor Node using Reinforcement Learning, Proc. of EMSOFT (2017)

98. Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura: "Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6 pages, Oct. (2017) (Acceptance ratio=29%) (to appear)

99. Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, and Mitaro Namiki, Building block multi-chip systems using inductive coupling Through Chip Interface, ISOCC2017, Seoul, (to appear) Nov. 2017

100. Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano, Scalable Deep Neural Network Accelerator Cores with Cubic Integration using Through Chip Interface, ISOCC2017, Seoul, (to appear) Nov. 2017

IV. 招待講演・チュートリアル

1. 中村宏, “プロセッサアーキテクチャのトレンド”, 第2回システムLSI琵琶湖ワークショップ，pp.27-33, 1998.11

2. 中村宏, “最近のプロセッサ・アーキテクチャ技術, 第5回 組込みシステム技術に関するサマーワークショップ, Sep. 2003

3. H.Nakamura, “System and Architecture Level Approaches”, ASP-DAC’06 Tutorial 3, Low Power / Low Leakage Technologies for Nanometer Era, Jan., 2006

4. 中村宏, “高性能/低消費電力プロセッサ・アーキテクチャ”, 情報処理学会関西支部大会VLSIシステム研究会, Oct, 2006

5. 中村宏, “アーキテクチャレベルの低消費電力化技術”, 電子情報通信学会2007年総合大会企画講演, Mar,　2007

6. 中村宏, “革新的電源制御による次世代超低電力高性能システムの実現へ向けて”, 東京工業大学計算世界観ワークショップ＃４：高性能計算における超省電力化, Dec, 2007

7. 中村宏, “高性能低消費電力プロセッサの実現技術　−回路技術とアーキテクチャの協調−”, 情報処理学会第70回全国大会、特別セッション（4）：地球にやさしい情報システム −持続可能なIT社会を目指して−、Mar, 2008

8. H. Nakamura, “Power Wall Problem: How to Make a Breakthrough? ~ Challenges and Opportunities for Architecture and Circuit-Level Co-Design”, ISVLSI (IEEE Computer Society Annual Symposium on VLSI) 2009, May, 2009

9. 中村宏, “Power Wall問題へのブレークスルーを目指して〜リーク電力削減への試み〜”, 情報処理学会創立50周年記念(第72回)全国大会特別セッション「未来を切り拓く最先端VLSIテクノロジー」3月9日, 2010

10. 中村宏、パネル “次のスパコンハードウェアはどう作っていく？”（パネリスト）、第2回戦略的高性能計算システム開発に関するワークショップ、2010年11月27日

11. 中村宏、パネル “基盤ソフトウェアの課題、研究開発アプローチ、マイルストーン「システムソフトウェアとアーキテクチャ」”（パネリスト）、第3回戦略的高性能計算システム開発に関するワークショップ、2011年2月5日

12. 中村宏、パネル “将来のスーパーコンピューティングへの挑戦”（パネリスト）、「これからのスーパーコンピューティング技術の展開を考える」シンポジウム（文部科学省主催）、東京大学、2011年6月28日

13. “Do Game chips contribute to High Performance Computing?”, Panel of IEEE Symposium on COOLChips V, 2002 (panelist)

14. “What is the future COOL and High-performance architecture?” Panel of IEEE Symposium on COOLChips VI, 2003 (moderator)

15. “How to solve the power wall problem of supercomputing (in 2015)?” Panel of International ACM Symposium on High Performance Distributed Computing (HPDC2009) (Panelist)

16. ノーマリオフコンピューティングによる低消費電力化への挑戦, 情報処理学会アーキテクチャ研究会パネル（モデレータ）情報処理学会研究報告, Vol.2012-ARC-198, No. 8, (2012-01-12)

17. ノーマリーオフコンピューティングの実現へ向けて，招待講演、電子情報通信学会VLD/CAS/MSS/SIP 共催研究会，IEICE信学技報, CAS2012-22, VLD2012-32, SIP2012-54, MSS2012-22, pp. 121 (2012/07/03)

18. Challenge for Zero Stand-by Power Management: -Road-map to the "Normally-Off Computing" , Panel of ASSCC 2012 (The 8th IEEE Asian Solid-State Circuits Conference), Moderator

19. ノーマリーオフコンピューティングへの挑戦，招待講演、電子情報通信学会VLD/CPSY/RECONF 共催研究会，IEICE信学技報, vol. 112, no. 376, CPSY2012-62, pp. 37-37, 2013年1月(VLD2012-113, CPSY2012-62, RECONF2012-67)

20. H. Nakamura, “Challenges and Opportunities of Normally-Off Computing”, 13th International Forum on Embedded MPSoC and Multicore, Keynote 16/July, 2013

21. H. Nakamura, T. Nakada, S. Miwa, (Invited Paper) Normally-Off Computing Project : Challenges and Opportunities, The 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session 1S-1, pp.1--5, Jan. (2014)

22. H. Nakamura, “Normally-Off Computing for Sensor-Net Applications”, Forum F5: Low-Power Radios for Sensor Networks, ISSCC2014, Feb. 2014

23. 中村宏, “IoT時代を切り拓くノーマリーオフ技術”, 第１回新産業技術促進検討会（モノづくり日本会議）2014/9/3

24. 中村宏, “持続可能なHPC基盤の構築へ向けて”, 第十四回PCクラスタシンポジウム, (2014/12/12)

25. H. Nakamura (panelist) “Panel Discussion: Challenges in the Era of Big-Data Computing”, ASP-DAC2015, January 21, 2015

26. H. Nakamura (to appear) Short course on "Analog and Digital Circuit Design for IoT Swarms“ Symposium on VLSI Circuits 2015 (16, June)

V. 解説

1. 中村宏, “特集「計算物理学と超並列計算機 - CP-PACS計画 -」の編集にあたって”, 情報処理学会誌, pp.10, Vol. 37, No.1, 1996

2. 中澤喜三郎, 中村宏, 朴泰祐, “超並列計算機CP-PACSのアーキテクチャ”, 情報処理学会誌, pp.18-28, Vol. 37, No.1, 1996

3. 中村宏, “たかがメモリされどメモリ”, 情報処理学会誌, pp.942-943, Vol. 40, No.9, 1999

4. 中村宏, “CPUのトレンド”, bit, pp.2-3, Vol.32, No.1, 2000 (共立出版)

5. 中村宏, “特集 「新世代マイクロプロセッサアーキテクチャ」 1.アーキテクチャ基盤技術 4.メモリ混載プロセッサメモリ”, 情報処理学会誌, pp.1118-1123, Vol.46 No.10, 2005

6. 中村宏, “研究会千夜一夜：これからもっと楽しい計算 機アーキテクチャ”, 情報処理学会誌, pp.390-391, Vol.48, No.4 2007

7. 中村宏, “未来を切り拓く最先端 VLSI テクノロジー : 3.Power Wall問題へのブレークスルーを目指して-リーク電力削減への試み- ”, 情報処理学会誌, pp.855-860, Vol.51, No.8, 2010

8. 清水徹, 冨嶋茂樹, 中村宏, コンピュータシステムを創り出したエレクトロニクス, 電子情報通信学会誌, Vol.100, No.9, pp.884-889, 2017