Toshiya Komoda
[English/Japanese]
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Affiliation

Graduate School of Information Science and Technology. The University of Tokyo.
Nakamura Laboratory.

Research Interest

Energy efficient computing system. Directive based GPU compiler. OpenACC. Heterogeneous task scheduling. Power management techniques, including DVFS and power gating.

Education

2004 -- 2008 (Bachelar) The University of Tokyo, Department of Engineering.
2008 -- (PhD) Graduate School of Information Science and Technology, The University of Tokyo.
2011〜 JSPS Research Fellow (DC1)

E-mail (Please replace _at_ with @)

komoda_at_hal.ipc.i.u-tokyo.ac.jp

Refereed Paper

  1. Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Matsunaga Kensaku, Kudo Masaru, Kimiyoshi Usami, Toshiya Komoda and Hiroshi Nakamura. "Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors", In the Proceedings of the Design, Automation and Test in Europe 2014 (DATE'14), Mar. 2014 (to appear).
  2. Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura. "Power Capping of CPU-GPU Heterogeneous Systems through Coordinating DVFS and Task Mapping", In the Proceddings of the 31st IEEE International Conference on Computer Design (ICCD'13), pp.349-356, Oct. 2013. PDF
  3. Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura and Naoya Maruyama. "Integrating Multi-GPU Execution into an OpenACC Compiler", In the Proceedings of the 42nd International Conference on Parallel Processing (ICPP'13), pp.260--269, Oct. 2013. PDF
  4. Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura. "Communication Library to Overlap Computation and Communication", In the Proceedings of the 17th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS'12, Workshop Conjunctioned with IPDPS'12), pp.567--573, May. 2012. PDF
  5. Toshiya Komoda, Hiroshi Sasaki, Masaaki Kondo and Hiroshi Nakamura. "Compiler Directed　Fine Grain Power Gating for Leakage　Power Reduction in Microprocessor Functional Units", In the Proceedings of the 7th Workshop on Optimizations for DSP and Embedded Systems(ODES'09, Workshop Conjunctioned with CGO'09), , pp.39--48, Mar. 2009. PDF